Reset, Clear and Default Configuration
Global Reset
Global Reset is performed at power-on of the module or via software by write access at register address 0xEF24
(whatever 32-bit value can be written). It allows to clear the data off the Output Buffer, the event counter and
performs a FPGAs global reset, which restores the FPGAs to the default configuration. It initializes all counters to their
initial state and clears all detected error conditions.
Memory Reset
The Memory Reset clears the data off the Output Buffer.
The Memory Reset can be forwarded via a write access at register address 0xEF28 (whatever 32-bit value can be
written).
Timer Reset
The Timer Reset allows to initialize the timer which allows to tag an event. The Timer Reset can be forwarded with a
pulse sent to the front panel GPI input (leading edge sensitive).
To Next Page
Loading...