Casio A-10 - Page 29

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No. Pin Name In/Out Pull-Up/Down 3V/5V Function To/From
71 RXDSH O 3 V RXD1 signal from CPU CPU
72 CS4B I 3 V Chip select CPU
74 PCMWAKEB O 3 V PCMCIA wake-up signal SYSTEM LSI
75 PCMIRQB O 3 V Interrupt signal for PCMCIA SYSTEM LSI
76 A24 I 3 V Address CPU
77 A23 I 3 V Address CPU
78 A22 I 3 V Address CPU
79 A21 I 3 V Address CPU
80 RESETB I 3 V RESETB signal SYSTEM LSI
82 V5IOIS16B I 5 V Write protect signal Card
83 A20 I 3 V Address CPU
84 A19 I Down 3 V Address CPU
85 A18 I Down 3 V Address CPU
86 A17 I Down 3 V Address CPU
87 A16 I Down 3 V Address CPU
88 A15 I Down 3 V Address CPU
89 A14 I Down 3 V Address CPU
92 MCLOCK I 3 V Clock CPU
93 BREQB I 3 V BREQB signal SYSTEM LSI
94 A13 I Down 3 V Address CPU
95 A12 I 3 V Address CPU
96 A11 I 3 V Address CPU
97 A10 I 3 V Address CPU
98 A9 I 3 V Address CPU
99 A8 I 3 V Address CPU
100 A7 I 3 V Address CPU
101 A6 I 3 V Address CPU
103 A5 I 3 V Address CPU
104 A4 I 3 V Address CPU
105 A3 I 3 V Address CPU
106 A2 I 3 V Address CPU
107 A1 I 3 V Address CPU
108 A0 I Down 3 V Address CPU
110 SIFENB O 3 V 9-pin RXD1 control RS232C
111 SIFSHUTB O 3 V RXD1 signal for CPU CPU
112 RXD3 I 5 V 3-pin RXD signal Serial
113 TXD3B O 5 V 3-pin TXD signal Serial
114 V5A19 O 5 V Address Card
115 V5A14 O 5 V Address Card
116 V5A18 O 5 V Address Card
118 V5A13 O 5 V Address Card
119 V5A17 O 5 V Address Card
120 V5A8 O 5 V Address Card
121 V5IOWRB O 5 V I/O write signal Card
122 V5A9 O 5 V Address Card
123 V5A11 O 5 V Address Card
124 V5A10 O 5 V Address Card
125 ICIOWRB I Up 3 V I/O write signal CPU
128 V5D15 I/O 5 V Data Card
129 V5CE1B O 5 V Chip enable Card
130 V5D14 I/O 5 V Data Card
131 V5D7 I/O 5 V Data Card
132 V5IORDB O 5 V I/O read signal Card
133 V5D13 I/O 5 V Data Card
134 CD1B I 5 V Card detect Card
135 V5D6 I/O 5 V Data Card
136 V5D12 I/O 5 V Data Card
139 V5D5 I/O 5 V Data Card
140 V5D11 I/O 5 V Data Card
141 V5D4 I/O 5 V Data Card
142 V5D3 I/O 5 V Data Card
143 V50EB O 5 V Output enable signal Card
144 V5CE2B O 5 V Chip enable Card