Casio A-10 - Lsi;IC Data; Mb87 A908 A (System Lsi; U3)

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No. Pin Name In/Out Pull-Up/Down Function To/From
1 VDET3B I Battery detecting signal (Off) Q52 (Detector)
2 VDETS I Backup battery detecting signal (Message) Q37 (Detector)
4 VDET2R I NiMH detecting signal (Off) Q2 (Detector)
5 A1 I/O Down Address
6 A2 I/O Down Address
7 A3 I/O Down Address
8 A4 I/O Down Address
9 A5 I/O Down Address
10 A6 I/O Down Address
11 A7 I/O Down Address
13 A8 I/O Down Address
14 A9 I/O Down Address
15 A10 I/O Down Address
16 A11 I/O Down Address
17 A12 I/O Down Address
18 A20 I/O Down Address
19 A21 I Down Address
20 A22 I Down Address
21 A23 I Down Address
23 A24 I Down Address
24 A25 I Down Address
25 PCMIREQB I Interrupt signal to PCMCIA GA
26 PCMWAKEB I Wake-up signal to PCMCIA GA
27 CE0ROMB O Chip select ROM
28 CE1ROMB O Chip select ROM
29 OEROMB O Output enable ROM
30 FlSHRTB O Reset signal for Flash
31 PRESETB O Reset signal GA
33 CASLHB I CASLH signal to CPU CPU
34 CASLLB I/O CASLL/OE signal from CPU CPU
35 RASB I/O RAS/CE signal for CPU CPU
36 RDB I Up Read signal from CPU CPU
37 WRHB I/O Up WE1 signal from CPU CPU
38 WRLB I/O Up WE0 signal from CPU CPU
39 RDWRB I/O Up RD/WRB signal from CPU CPU
40 CS0B I Up CS0 signal from CPU (ROM) CPU
41 CS4B I Up CS4 signal from CPU (SYSTEM LSI) CPU
42 TEST1 I Test pin
43 TEST2 I Test pin
44 TEST3 I Test pin
45 D0 I/O Down Data bus
46 D1 I/O Down Data bus
48 D2 I/O Down Data bus
49 D3 I/O Down Data bus
50 D4 I/O Down Data bus
51 D5 I/O Down Data bus
52 D6 I/O Down Data bus
53 D7 I/O Down Data bus
54 D8 I/O Down Data bus
55 D9 I/O Down Data bus
57 D10 I/O Down Data bus
58 D11 I/O Down Data bus
59 D12 I/O Down Data bus
60 D13 I/O Down Data bus
61 D14 I/O Down Data bus
62 D15 I/O Down Data bus
63 CAS0LB O CAS signal for DRAM DRAM
LSI/IC DATA
MB87A908A (SYSTEM LSI / U3)