Casio A-10 - Mbcg25942-5110 (Gate Array; U4)

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No. Pin Name In/Out Pull-Up/Down 3V/5V Function To/From
1 VDD1 I 5 V +5 V source Power
2 V5WEB O 5 V Write signal Card
3 V5A20 O 5 V Address Card
4 BSYB I 5 V Busy ready Card
5 V5A21 O 5 V Address Card
6 V5A16 O 5 V Address Card
7 V5A22 O 5 V Address Card
8 V5A15 O 5 V Address Card
10 V5A23 O 5 V Address Card
11 V5A12 O 5 V Address Card
12 V5A24 O 5 V Address Card
13 V5A7 O 5 V Address Card
14 V5A25 O 5 V Address Card
15 V5A6 O 5 V Address Card
16 V5A5 O 5 V Address Card
17 ICIORDB I Up 3 V I/O read signal CPU
20 RESET O 5 V Reset signal Card
21 V5A4 O 5 V Address Card
22 V5A3 O 5 V Address Card
23 INPACKB I 5 V Input response Card
24 V5A2 O 5 V Address Card
25 REGB O 5 V Attribute memory select Card
26 V5A1 O 5 V Address Card
27 BVD2 I 5 V Battery detect Card
28 V5A0 O 5 V Address Card
29 BVD1 I 5 V Battery Detector Card
31 CD2B I 5 V Card detect Card
32 V5D8 I/O 5 V Data Card
33 V5D1 I/O 5 V Data Card
34 V5D9 I/O 5 V Data Card
35 V5D2 I/O 5 V Data Card
36 V5D10 I/O 5 V Data Card
38 MDCD O 3 V Port
39 D15 I/O 3 V Data CPU
40 D14 I/O 3 V Data CPU
41 D13 I/O 3 V Data CPU
42 D12 I/O 3 V Data CPU
43 D11 I/O 3 V Data CPU
44 D10 I/O 3 V Data CPU
46 V5WAITB I 5 V Wait signal Card
47 D9 I/O 3 V Data CPU
48 D8 I/O 3 V Data CPU
49 D7 I/O 3 V Data CPU
50 D6 I/O 3 V Data CPU
51 D5 I/O 3 V Data CPU
52 D4 I/O 3 V Data CPU
53 D3 I/O 3 V Data CPU
56 D2 I/O 3 V Data CPU
57 D1 I/O 3 V Data CPU
58 D0 I/O 3 V Data CPU
59 CS6B I Up 3 V Chip select CPU
60 CE2B I Up 3 V Chip enable CPU
61 RDB I 3 V Output enable CPU
62 WAITB O 3 V Wait signal CPU
63 WRHB I 3 V Write signal CPU
64 V5D0 I/O 5 V Data Card
67 MODE I 3 V Port
68 RDWRB I 3 V Read/Write signal CPU
69 IOIS16B O 3 V Write protect CPU
70 TXDSH I 3 V TXD1 signal for CPU CPU
MBCG25942-5110 (GATE ARRAY / U4)