Casio FE-700 MEX

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6-7. RAM / ROM / Fiscal ROM bank selection circuit
This circuit is used for address decoder for mamory.
A11
IOGATE
GATE
F. ROM1
F.ROM2
HC32A
HC32A
HC32A
1
2
12
13
3
11
IC22
IC22
IC22
HC32A
9
10
8
IC22
GND
R123
56K
VCC
C64
100P
PGM
PGM
EEPCE
9
Memory Map
C000
A000
8000
6000
4000
2000
0000
RAM BANK select
area (4K)
E000
RAM common area
(8K)
EP ROM
Common (16K)
Mask ROM
(16K)
F000
F800
Internal RAM
(High speed access)
288 bytes
Internal RAM
(High speed access)
Short direct area
192 bytes
FE20
FFFF
FA80
Internal RAM
(High speed access)
Outer I/O area
F000
General purpose
register 32 bytes
Special function
register (SFR)
256 bytes
Direct access
window for
Fiscal ROM
(2K)
FEE0
FFF0
Bank
0
Bank
5
Bank
4
Bank
2
Bank
1
Bank
3
EP ROM
Bank select area
(16K)
FAE0
FD00
Buffer RAM 32 bytes
FAC0
KI signal port (F800,F801)
000000
00001
00010
00011
00100
00101
00110
Bank
29
11101
RAM256K
RAM 1M