Technical description
4-32 HF SSB Transceiver 9323/9360/9390/9780 Technical Service Manual
ALC control
The Automatic Level Control is provided from:
• forward power
• reflected power
• output stage collector swing
• battery voltage
• heatsink over temperature
• transmit/receive and filter relay failure
All the ALC control inputs, except for relay failure detection (detailed later), are
applied to V8 to V11. The ORed output is connected via R30 to the positive input
pin of the ALC level comparator IC3/B pin 5. The reference voltage to pin 6 is
software controlled by the microprocessor IC101.
The PA-PWM line from the microprocessor IC101 pin 5 [1 04-02976 Sheet 1]
outputs a programmed mark:space ratio. This is applied via a filter network
(R106, C104, R105 and C103) to the buffer amplifier IC107/A pin 3.
The DC level at the output represents the average mark:space ratio set by the
microprocessor. This is applied via R36 to the reference input of IC3/B pin 6 on
the PA and Filter PCB [1 04-02973 and 04-03096]. The control voltage ranges
between 2 to 5 V. This is limited by the resistor divider network R32, R33 and
R34 (NTC) to between 3.0 to 3.8 V at the reference input of IC3/B pin 6. This
allows the microprocessor to reduce the PA output at the higher operating
frequencies and ensures that the intermodulation distortion remains within the
specified limits.
In the absence of any ALC inputs, the output of IC3/B holds the base of V13 to
the reference voltage on pin 6 (3.0 to 3.8 V). With the base of V14 referenced to
5 V, V13 will be cut off, setting V14 to maximum gain. If an ALC control signal
causes any of the transistors V8 to V11 to conduct, it will result in the rise of the
output of IC3/B. This reduces the gain of V14 and thereby controls the gain of the
PA.
The output voltage of the RF bridge (T1, L3 and R2) and capacitor divider (C6,
C3, C4 and C5) is rectified by D1 for the forward power and by D2 for the
reflected power.
The output of the forward rectifier D1 is applied via R22 to the input of V8. The
resistor R22 and the sum of the resistors between the base of V8 and ground, form
a resistor divider network. This determines the nominal PEP output level when
matched to a 50 Ω load.
For high power, the sum of the lower section of the divider chain consists of R21,
the parallel value of R15 and R16 (SOT), and R19. The resistors R17 (SOT) and
R18 are shorted out by the FET switch V7 (+5 V on gate) and do not contribute to
the chain. The nominal high power output, which is measured at low frequency, is
set by R16 (SOT).
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