Technical description
4-34 HF SSB Transceiver 9323/9360/9390/9780 Technical Service Manual
Selective calling
All the selective calls are sent as Frequency Shift Keying (FSK) signals and
normally use 1700 Hz and 1870 Hz at a rate of 100 baud.
Calibration
The phase lock loop Selcall FSK Decoder IC302 on the Microprocessor and
Audio PCB [1 04-02976 Sheet 3] has a Voltage Controlled Oscillator (VCO)
whose frequency is set by C310, R315 and the DC volts across R317.
The Pulse Width Modulation Output (S-PWM line) from the microprocessor
IC101 pin 4 [1 04-02976 Sheet 1], is filtered by R155 and C314 (see Sheet 3) to
produce a DC voltage across R317. The level of the voltage is set by the
mark:space ratio of the Pulse Width Modulation Output from the microprocessor
and will determine the final frequency of the VCO.
For the Selcall FSK Decoder IC302 to perform correctly, it is necessary for the
two selcall frequencies to be centred on the VCO frequency (e.g. for 1700 Hz and
1870 Hz the centre frequency = 1785 Hz). This is automatically checked and
calibrated every time the power is applied to the transceiver.
The procedure for FSK is:
• At switch on, the microprocessor IC101 [1 04-02976 Sheet 1] programs a test
tone from the tone generator IC106 pin 17 at the centre frequency of the two
selcall working frequencies. The microprocessor also provides a Pulse Width
Modulation Output (S-PWM line on pin 4) to produce a predetermined DC
voltage across R317 [1 04-02976 Sheet 3]. This sets the VCO to within the
operating frequency band.
• The test tone is applied via R135A, C120 and R136 to the input of the dual
active BPF network IC301A/B and associated components [1 04-02976
Sheet 3]. The filter has a 3 dB bandwidth of 400 Hz centred on 1785 Hz. The
filtered output (pin 7) is applied to the FSK Decoder IC302 pin 2.
• The loop phase detector output (pin 11) produces an AC output with a DC
offset. This is applied to an active data filter IC303/A to remove the AC
component. The remaining DC voltage at the output (pin 1 FSK"V" line) is
connected via divider R120 and R122 to an A/D input of the microprocessor
IC101 pin 62. There is also a reference voltage derived from IC302 pin 10
(REF"V" line). This is connected via resistor divider R119 and R121 to a
second A/D input of the microprocessor IC101 pin 63.
• The microprocessor IC101 compares the two DC levels FSK"V" and REF"V".
IC101 adjusts the mark:space ratio of the Pulse Width Modulation Output (S-
PWM line) until the difference voltage equals zero. This sets the VCO to half
way between the two operating FSK tones. For fast calibration on power up,
the microprocessor retains this setting in the E
2
PROM IC108.
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