Dwin T5L ASIC Series User Manual

T5L_ASIC Development Guide
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3.1 Initial Configuration
When the 8051 kernel is powered on, the special function register (SFR) in the following table must
be initialized correctly.
SFR name
Address
Initial values
Instructions
CKON
0X8E
0X00
CPU runs in 1T mode
T2CON
0XC8
0X70
Configure extended interrupt system;
configure timer T2 to run in autoload mode
DPC
0X93
0X00 or 0x01
The change mode of DPTR after MOVX instruction operation must
be configured to 0x00 if developed with C51.
0x00: No change. 0x01: DPTR=DPTR+1. 0x03: DPTR=DPTR-1.
PAGESEL
0X94
0X01
64KB code space
D_PAGESEL
0X95
0X02
32KB RAM space accessed by MOVX: 0x8000-0xFFFF
MUX_SEL
0XC9
0x60 or configuration
according to
application needs
Peripheral multiplexing selection:
.7 1 = CAN interface leads to P0.2, P0.3, 0 = CAN interface does
not lead out, and it works as an IO interface;
.6 1 = UART2 interface leads to P0.4, P0.5, 0 = UART2 interface
does not lead out, and it works as an IO interface;
.5 1 = UART3 interface leads to P 0.6, P 0.7, 0 = UART3 interface
does not lead out, and it works as an IO interface;
.4-.2 Reserved;
.1 WDT control 1=open 0=close;
.0 WDT feed dog, 1=feed the dog one time(The WDT count
becomes zero, and the watchdog's overflowing time is one
second. );
PORTDRV
0XF9
0x01
Driver capability configuration of IO port output mode.
0x00=4mA
0X01=8mA
0X02=16mA
0X03=32mA
RAMMODE
0XF8
0X00
DGUS variable memory access interface control

Dwin T5L ASIC Series Specifications

General

Frequency	250MHz
Touch Panel Type	Resistive/Capacitive
Operating Temperature	-20°C to 70°C
Voltage Range	3.3V
Touch Controller	Integrated
Package	LQFP128
Operating System	DGUS II
Interface	UART, GPIO

Summary

1 Summary

2 Hardware Description

2.1 PIN Definition

Details the pin arrangement and functions of the T5L ASIC in ELQFP128 package.

2.2 Packaging Dimension

Provides detailed dimensions and tolerances for the ELQFP128 package.

2.3 Basic Performance Parameters

Lists key electrical and operational parameters for the T5L ASIC.

2.4 Notices for Hardware Design

Offers essential guidelines and precautions for designing hardware with the T5L ASIC.

3 OS CPU

3.1 Initial Configuration

Details the initial configuration of special function registers (SFRs) for the 8051 kernel.

3.2 Memory

Explains the different types of memory available: Code, Variable, Data, and Extended SFR registers.

3.3 Mathematical Operating Unit(MDU)

Introduces the hardware MAC and divider for improved computing power in the T5L.

3.4 Timer

Describes the three timers (T0/T1/T2) available in the T5L OS 8051.

3.5 Watchdog Timer(WDT)

Explains the software watchdog timer for system monitoring and reset.

3.6 IO

Details the three 8-bit parallel ports and one 4-bit parallel port, totaling 28 IO ports.

3.7 UART

Details the configuration and settings for UART interfaces: UART2, UART3, UART4, and UART5.

3.8 CAN

Details the SFRs associated with the CAN interface.

3.9 Interrupt System

Covers interrupt control SFRs and priority configuration for the T5L OS CPU.

3.10 T5L ASIC 8051 Instruction Set

Lists the instruction format, length, and cycles for the T5L ASIC 8051 instruction set.

4 Simulation Debug

5 EK043 Evaluation Board