T5L_ASIC Development Guide
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2.4 Notices for Hardware Design
(1) The core power voltage must be stable, otherwise it will lead to abnormal CPU operation.
(2) Reset is recommended to be handled by a low-level reset IC like SGM809S, instead of a simple
RC reset circuit. The T5L has a built-in watchdog (WDT) for each CPU core, so there is no need for
an external WDT IC.
(3) When designing for dual panel applications, connect a 470pF in parallel with 104 (or 105) filter
capacitors as close as possible to the IC supply pins to reduce noise emission.
(4) When IO input signal is over 0.3V of VIO voltage, IO must be protected by voltage divider or
clamp, otherwise it may cause abnormal signal or damage IC.
(5) All IO ports are floating input when they are configured as input mode, without internal pull-up or
pull-down.
All IO ports are in the input mode during the reset. If they are output, they can be pulled down or
pulled up externally to ensure that the reset has a definite level.
(6) The 4-bit bus speed of T5L and external SPI Flash is 100MHz, and thus The wiring should be as
close as possible and 470pF must be arranged on the power pins of the SPI Flash in parallel with
105 filter capacitor.
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