Dwin T5L ASIC Series - Table of Contents

T5L_ASIC Development Guide
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D WI N T echnology
Pro f essional , Credi t able , Success f ul
Contents
1 Summary ........................................................................................................................................... 3
2 Hardware Description........................................................................................................................ 5
2.1 PIN Definition ................................................................................................................................. 5
2.2 Packaging Dimension .................................................................................................................. 10
2.3 Basic Performance Parameters ................................................................................................... 11
2.4 Notices for Hardware Design ....................................................................................................... 12
3 OS CPU .......................................................................................................................................... 13
3.1 Initial Configuration ...................................................................................................................... 14
3.2 Memory ........................................................................................................................................ 15
3.2.1 Code Memory(64KBytes) .......................................................................................................... 15
3.2.2 Variable Memory(256KBytes) .................................................................................................... 16
3.2.3 Data Memory(32KBytes) ........................................................................................................... 18
3.2.4 Extended SFR Register ............................................................................................................ 19
3.3 Mathematical Operating Unit(MDU) ............................................................................................. 20
3.4 Timer ............................................................................................................................................ 22
3.5 Watchdog Timer(WDT) ................................................................................................................ 24
3.6 IO ................................................................................................................................................. 25
3.7 UART ............................................................................................................................................ 27
3.7.1 UART2 ...................................................................................................................................... 27
3.7.2 UART3 ...................................................................................................................................... 28
3.7.3 UART4 ...................................................................................................................................... 29
3.7.4 UART5 ....................................................................................................................................... 30
3.8 CAN ............................................................................................................................................. 31
3.9 Interrupt System ........................................................................................................................... 33
3.9.1Interrupt Control SFR ................................................................................................................. 33
3.9.2 Interrupt Priority ......................................................................................................................... 34
3.10 T5L ASIC 8051 Instruction Set ................................................................................................... 30
4 Simulation Debug ............................................................................................................................ 32
5 EK043 Evaluation Board ................................................................................................................. 34