Dwin T5L ASIC Series User Manual

T5L_ASIC Development Guide
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3.2.3 Data Memory(32KBytes)
The OS 8051 CPU of T5L has 32KBytes RAM as data memory, corresponding to addresses 0x8000-
0xFFFF, and the related interface SFRs are listed below.
SFR name
Address
Instructions
DPC
0x93
DPTR change mode after MOVX instruction operation.
DPC=0X00:DPTR remains unchanged after MOVX instruction operation. If developed using
C51, DPTR must be configured as 0x00
DPC=0X01 After MOVX instruction operation, DPTR=DPTR+1
DPC=0X03 After MOVX instruction operation, DPTR=DPTR-1
DPH
0X83
DPTR data pointer
DPL
0X82
The address space from 0x0000 to 0x7FFF prohibit using MOVX instructions to read and write,
which may cause code to run abnormally.
The T5L's MOVX instruction is 3 instruction cycles (3T, 14.5nS at 11.0592MHz crystal), and the DPC
can be configured with DPTR auto increment (or decrement) mode, making the T5L much faster than
the standard 8051 for reading and writing data memory, especially for inverse order memory read
and write applications.
Example
MOV
DPC,#01H
;DPTR++
MOV
DPTR,#8000H
MOVX
A,@DPTR
;A=@8000
MOVX
A,@DPTR
;A=@8001, DPTR=8002 after reading

Dwin T5L ASIC Series Specifications

General

Brand	Dwin
Model	T5L ASIC Series
Category	Control Unit
Language	English