Table of Contents User's Manual
BAB 740
VIII
Table 37: Memory Address Map
(default used by VxWorks) ................................... 7—8
Table 38: IDSEL Connection................................................ 7—9
Table 39: CPU Drive Strength Configuration (J101, J102) .. 7—9
Table 40: CPU PLL Configuration (J103...J106) ................ 7—10
Table 41: System Clock (J111, J112, J113)....................... 7—10
Table 42: MPC106 PLL Configuration (J110...J107) ......... 7—11
Table 43: Cache Size (J601, J602, J603) .......................... 7—11
Table 44: Hardware Debugger Configuration (J1301) ....... 7—12
Table 45: Revision EEPROM Write Protection (J1302) ..... 7—12
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