Figure 157: PSB timer setting guidelines 282
Figure 158: Out of Step detection characteristic 283
Figure 159: Out of Step logic diagram 285
Figure 160: OST setting determination for the positive sequence resistive component OST R5 287
Figure 161: OST R6max determination 288
Figure 162: Example of timer reset due to MOVs operation 290
Figure 163: Autoreclose sequence for a Transient Fault 300
Figure 164: Autoreclose sequence for an evolving or permanent fault 301
Figure 165: Autoreclose sequence for an evolving or permanent fault - single-phase operation 301
Figure 166: Key to logic diagrams 303
Figure 167: Autoreclose System Map - part 1 304
Figure 168: Autoreclose System Map - part 2 305
Figure 169: Autoreclose System Map - part 3 306
Figure 170: Autoreclose System Map - part 4 307
Figure 171: Autoreclose System Map - part 5 308
Figure 172: CB State Monitor logic diagram (Module 1) 318
Figure 173: Circuit Breaker Open logic diagram (Module 3) 319
Figure 174: CB In Service logic diagram (Module 4) 319
Figure 175: Autoreclose OK logic diagram (Module 8) 320
Figure 176: Autoreclose Enable logic diagram (Module 5) 320
Figure 177: Autoreclose Modes Enable logic diagram (Module 9) 322
Figure 178: Force Three-phase Trip logic diagram (Module 10) 322
Figure 179: Autoreclose Initiation logic diagram (Module 11) 324
Figure 180: Autoreclose Trip Test logic diagram (Module 12) 324
Figure 181: Autoreclose initiation by external trip or evolving conditions (Module 13) 325
Figure 182: Protection Reoperation and Evolving Fault logic diagram (Module 20) 326
Figure 183: Fault Memory logic diagram (Module 15) 326
Figure 184: Autoreclose In Progress logic diagram (Module 16) 327
Figure 185: Autoreclose Sequence Counter logic diagram (Module 18) 328
Figure 186: Single-phase Autoreclose Cycle Selection logic diagram (Module 19) 328
Figure 187: Three-phase Autoreclose Cycle Selection logic diagram (Module 21) 329
Figure 188: Dead time Start Enable logic diagram (Module 22) 330
Figure 189: Single-phase Dead Time logic diagram (Module 24) 331
Figure 190: Three-phase Dead Time logic diagram (Module 25) 332
Figure 191: Circuit Breaker Autoclose Logic Diagram (Module 32) 333
Figure 192: Prepare Reclaim Initiation Logic Diagram (Module 34) 334
Figure 193: Reclaim Time logic diagram (Module 35) 334
Figure 194: Successful Autoreclose Signals logic diagram (Module 36) 335
Figure 195: Autoreclose Reset Successful Indication logic diagram (Module 37) 335
Figure 196: Circuit Breaker Healthy and System Check Timers Healthy logic diagram (Module 39) 336
P543i/P545i Table of Figures
P54x1i-TM-EN-1 xxix