4 Central Functions HIMatrix
Page 24 of 72 HI 800 023 E Rev. 1.01
Properties of the F60 CPU 01 processor module
Two synchronous microprocessors (processor 1 and processor 2).
Each microprocessor has its own RAM memory.
Testable hardware comparators for all external accesses of both microprocessors.
In the event of an error the watchdog is set to a safe state.
Flash EPROM for operating system and user program, suitable for at least 100,000
memory cycles.
Data memory in NVRAM.
Multiplexer for connecting I/O bus, dual port RAM (DPR).
Back-up battery or Goldcap for date/time.
Communication processor for fieldbus and Ethernet connections.
Interface for data transfer between F3 controllers, F60 and the PADT, based on
Ethernet.
Optional interface(s) for data exchange via fieldbus.
LEDs for indicating the system statuses.
I/O bus logic for connection to I/O modules.
Safe watchdog (WD).
Monitoring of power supply units, testable (3.3 V = / 5 V = system voltages).
4.3 Self-Tests
The following section explains in note form the most important self-test routines of
controllers' safety-related processor modules and the coupling to the I/O level.
4.3.1 Microprocessor Test
The following is tested:
All commands and addressing modes used.
The writability of the flags and the commands generated by them.
The writability and crosstalk of the registers.
4.3.2 Memory Areas Test
The operating system, user program, constants and parameters as well as the variable
data are saved in memory areas of both processors and are tested by a hardware
comparator.
4.3.3 Protected Memory Areas
The operating system, user program and parameter area are each stored in a memory.
They are protected by write protection and a CRC test.
4.3.4 RAM Test
A write and read test is performed to check the modifiable RAM areas, in particular stuck-at
and crosstalk.
4.3.5 Watchdog Test
The watchdog signal switches off if it is not triggered from both CPUs within a defined time
window and also if the test of the hardware comparator fails. An additional test determines
whether the watchdog signal is able to switch off.
4.3.6 Test of the I/O Bus Inside the Controller:
The connection between the CPU and the associated inputs and outputs (I/O modules) is
tested.
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