Transmission Line Theory Applied to Digital Systems
Transmission Line Design
11-8
The voltage and current at points A and B are the same initially, as shown in
Figure 11-4. At t = 0, the voltage at the source switches from a logic 0 to a logic
1 level. The voltage term, v
A
(t), in equation 1 is:
where: (v’
OH
- v’
OL
) = E
S
(t) = internal voltage swings in the circuit = ∆V
INT
Therefore, at time t = 0 a voltage waveform, V = 0.81 V, and a current, I = 16.2
mA, travel down the line as shown in Figure 11-4 by the line from t = 0 to t =
T
D
(T
D
is the time it takes for the wavefront to travel down the length of the
line). A line is drawn from t = T
D
to t = 2T
D
. Voltage and current values are as
indicated. Note that the reflected current is negative, indicating the current is
flowing back toward the source; the reflection coefficient for the current is a
minus one times the reflection coefficient for the voltage.
To find the voltage at point B for t = T
D
all the voltages entering and leaving
this point are summed. The same is done to determine the load current. The
process continues until the voltage at the load approaches the new steady state
condition in the example. This condition occurs when t = 3T
D
. (The steady
state logic 1 voltage is actually 1.13 V).
This example indicates that for a case in which the load resistor is 30% higher
than the characteristic impedance, 85 mV of overshoot and 10 mV of undershoot
would occur. Generally, as far as noise immunity is concerned, only the
undershoot need be considered. The typical noise immunity (or noise margin)
for a MECL circuit is greater than 200 mV. Since the undershoot in this example
was 10 mV, the typical noise immunity would exceed 190 mV. In actual system
design, typically more than 100 mV of undershoot can be tolerated. Regarding
overshoot, 300 mV can be tolerated, except in some early ac coupled flip-flops
(MECL I and II). This restriction insures that saturation of the input transistor
does not occur (if it did, the gate would slow down). If a 100 Ω load resistor
were used in Figure 11-4, the resulting overshoot would be about 220 mV and
the undershoot, about 80 mV. If the load resistor is twice the characteristic
impedance, the noise margin is typically 120 mV which is more than acceptable
for MECL circuits.
v
A
t
()
V
′
OH
V
′
OL
–
()
Z
o
Z
o
R
o
+
------------------
v
1
0.81 volts,===
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