Transmission Line Theory Applied to Digital Systems
Transmission Line Design
11-9
A slightly different situation can exist when the output of the MECL gate
switches from a logic 1 to a logic 0. The output of the MECL gate will turn off
if the termination resistor, R
L
, is somewhat larger than the characteristic
impedance of the line. For the conditions in Figure 11-4, the output transistor
of the MECL gate will turn off at t = 0 for the negative going transition, when
R
L
> 70 Ω.
An equation for the value for R
L
at which the gate will turn off can be derived
as follows. The maximum voltage change at point A in Figure 11-4, (due to
turning off the output transistor) is the product of the dc current in the line and
the characteristic impedance of the line:
The voltage at point A is also dependent on the internal resistance of the driving
gate R
o
and the internal logic swing.
Equating the two and solving for R
L
:
(6)
Thus for the conditions given in Figure 11-4, the output transistor will turn off at
The case for which the MECL output turns off is not in itself a serious problem,
although it makes a thorough analysis more difficult. Two reflection coefficients
must be used at the sending end and a piecewise approach used in determining
the voltage reflections.
∆
V
A
I
LINE
Z
o
()
V
′
OH
R
o
Z
o
+
------------------
Z
o
()
==
∆
V
A
Z
o
R
o
Z
o
+
------------------
∆
V
INT
()
=
R
L
V
′
OH
R
o
Z
o
+
()
∆
V
INT
------------------------------------ R
o
–=
t 0 when R
L
1.22 5 50+
()
0.9
-------------------------------5–70
Ω
is exceeded.== =