IBM 1 Series - Interrupt Presentation; Status after Power Transitions and Resets

Interrupt Presentation
CC3 Device End—Reported when the timer has decremented one more
than the specified number of time intervals (underflow). Also
reported when ‘external gate’ has been enabled and the timer
detects an underflow prior to the end of one complete external
gate cycle.
CC4 Attention—Reported only when an external gate cycle has been
completed prior to a timer underflow; ‘run state’ is reset.
CC6 Attention and Exception—Reported if the external gate cycle has
been completed and an overrun condition is present in the timer;
‘run state’ is reset (see CC2).
CC7 Attention and Device End—Reported when a timer has
underflowed prior to, or at the same time as, the completion of an
external gate cycle; ‘run state’ is reset.
The timers are prepared together and function as one preparable source.
Neither timer should be started unless the I-bit is on.
After the timers start, they post the first device-end interrupt in a time
interval corresponding to the specified count up to a maximum of one
more count. For example, if a count of hex 0003 is loaded (3 counts), the
actual time to the first device-end interrupt ranges from 3 to 4 times the
selected time base. This is because of the asynchronous nature of the
internal free-running oscillator or external-pulse train, with respect to the
program setting of ‘run state’ or the activation of ‘external gate.’ This
uncertainty must be taken into account only once each time a timer is
started.
There is also an uncertainty associated with the value of the timers when
measuring the duration of ‘external gate’ in pulse-duration applications.
This is because of the asynchronous nature of the ‘external gate’
deactivation, with respect to the internal clock or external pulse train. This
uncertainty is the time corresponding to +1 count in the timer value after
it is stopped.
Pulse-averaging applications that use a known fixed-time of ‘external gate’
activation and random pulses on the ‘customer clock’ input must also take
into account a +1 count uncertainty in the timer value after it is stopped
by the deactivation of ‘external gate.’
Status After Power Transitions and Resets
When a machine check occurs, or when a Halt I/O or Device Reset
command is executed, the timers are stopped, ‘run state’ is reset, the mode
register is reset, and any pending interrupt requests are reset. The prepare
field, including the I-bit, and the value in the timers are not reset.
When a system reset occurs, both timers are stopped, ‘run state’ is reset,
and the mode registers are reset. The values held in the timers and
auto-load registers are not reset. The prepare field, including the I-bit, is
reset.
When a power-on reset occurs, all resets caused by system reset occur; in
addition, the timers are reset to their maximum value (that is, all 1’s), and
the auto-load registers are set to their maximum value.
Timer Feature 3-9