IBM 1 Series - Processor I;O Channel Electrical Characteristics; Channel Signal Line Electrical Characteristics

Processor I/O Channel Electrical Characteristics
Channel Signal Line Electrical Characteristics
2-50
GA34-0033
Figure 2-21 shows the I/O channel at the backpanel in a tabular form.
Signal lines are identified in terms of direction, I/O pin assignment,
processor driver/receiver type, and active and quiescent levels. Special
reserved lines that are used for storage or floating-point are not listed.
The direction of a signal is indicated by an arrow. An arrow pointing to
the right indicates a signal from the processor; pointing to the left, from
the device. A line with double arrows indicates a bidirectional signal.
Signal levels and driver/receiver types are listed as they would appear at
the first and succeeding I/O attachment sockets, but not necessarily at
specific pins on the processors.
The active levels shown correspond to logical 1’s for address bus bits
O—15, data bus, condition code in, cycle indicators, poll identifier bits, and
status bus bits; these levels correspond to activation of tags and requests.
The quiescent levels are defined for the following conditions:
e The processor and I/O device are in the state that follows a system
reset.
e The Load key has not been pressed.
e No reset tags are active.
Under these conditions, there is no channel activity to or from the I/O
devices, storage, or floating-point.
Notes for Figure 2-21:
Address and data buses contain processor-dependent quiescent levels.
2. These lines are also driven by the 4952 and 4953 processors in
conjunction with the storage interface (driver/receiver type C-C).
3. Neither processor uses these bits; therefore, they are tied up to the
defined quiescent level at the processor.
4. There is no connection to this pin for the first I/O socket on either
the 4952 or the 4953 backpanel.
5. Power-on reset is driven directly by the power supply circuitry.
Neither the 4952 nor the 4953 backpanel connects to any of these
pins.
7. Neither the 4952 nor the 4953 processor uses status bus bit 2 (for
storage protect); therefore, this line is tied up to the defined quiescent
level.