IBM 1 Series - Input Sequence

Input Sequence
Figure 6-4 is a timing diagram for a typical input sequence.
An input sequence is executed as follows:
1.
to
Control lines __]
I/O active
Strobe (device)
Select response
Condition code in
Function, modifier, and device address bits are placed on their
appropriate lines.
The ‘I/O active’ tag is skewed (at least 200 nanoseconds) and
activated on the interface.
Upon recognition of an address compare and ‘I/O active,’ the device
raises the ‘select response’ tag. Once raised, this tag must be held
active at least until the fall of the ‘I/O active’ tag. ‘Data bus in’ and
‘condition code in’ must be active until ‘strobe’ becomes active or until
‘I/O active’ becomes inactive for the duration of the ‘select response’
tag.
‘Strobe’ is activated and dropped; however, if a parity error is detected
by the processor, this tag is not activated.
The ‘I/O active’ tag is deactivated.
Upon recognition of the absence of the ‘I/O active’ tag, the device
drops ‘select response,’ ‘condition code in,’ and ‘data bus in.’
Input sequence
Strobe > Q
>200 ns S15 ys
>5
ns
LO
/ /
<1.5 ps 7100 ns
¢|*
and data bus in
Figure 6-4. Input sequence timing diagram
Customer Direct Program Control (DPC) Adapter Feature 6-9