IBM 1 Series - Chapter 2. Processor I;O Channel; Introduction

Introduction
Chapter 2. Processor I/O Channel
Input/output devices communicate with the processor and main storage
devices through the processor I/O channel. Attachment of the devices to
the channel is through an I/O adapter or I/O attachment logic card.
The channel directs the flow of information between the I/O devices, the
processor, and main storage. A maximum of 256 devices can be logically
addressed.
The processor I/O channel supports the following basic types of
operations:
e Direct program control (DPC) operations—an immediate data transfer
is made between main storage and the device for each Operate I/O
instruction. The data may consist of one byte or one word. The
operation may or may not terminate with an interrupt.
e Cycle-steal operations—an Operate I/O instruction can initiate
cycle-stealing data transfers of up to 65,535 bytes (per device control
block) between main storage and the device. Cycle-steal operations are
overlapped with processing operations. Word or byte transfers, device
control block (DCB) chaining, burst mode, and program-controlled
interrupts can be supported.
e Interrupt servicing operations—four preemptive priority interrupt
levels are available to facilitate device service. The device-interrupt
level is assignable by the program, and the device-interrupt capability
can be masked under program control.
e Initial program load (IPL) operations—a record consisting of initial
instructions for the processor is read into storage from either a local
I/O device or from a host system.
The channel provides comprehensive error checking, including time-outs,
sequence checking, and parity checking. Reporting of errors, exceptions,
and status is accomplished by (1) recording condition codes in the
processor during execution of Operate I/O instructions, and (2) recording
condition codes and an interrupt information byte (IIB) in the processor
during interrupt acceptance. Additional status words may be used by the
device, as necessary, to describe its status.
The I/O channel is asynchronous and multidropped. Asynchronous means
that there are no timing restrictions inherent in the architecture. The
response from a given I/O device triggers the next sequential action rather
than a specified timing condition. (Time-out conditions for error detection
are not excluded.) An asynchronous channel allows the attachment of
devices that have various speeds and technologies over a wide range of
distances or delays.
All I/O channel signal lines are TTL-level compatible. This allows the user
freedom in the design of I/O channel attachments.
Processor I/O Channel 2-1