IBM 1 Series - Interrupt-Service Sequence

Interrupt-Service Sequence
Figure 6-5 is a timing diagram for a typical interrupt-service sequence.
This sequence is executed as follows:
1. The device address bits are placed on their appropriate lines.
2. The ‘interrupt service active’ tag is skewed (at least 200 nanoseconds)
and activated on the interface.
3. Upon recognition of an address compare and ‘interrupt service active,’
the device raises the ‘select response’ tag. Once raised, this tag must
be held active at least until the fall of the ‘interrupt service active’ tag.
‘Condition code in’ and ‘data bus in’ must be active for the duration of
the ‘select response’ tag or at least remain active until ‘strobe’ becomes
active.
4. ‘Strobe’ is activated and dropped. The I/O device must reset its
interrupt request at the leading edge of ‘strobe.’
The ‘interrupt service active’ tag is deactivated.
Upon recognition of the absence of the ‘interrupt service active’ tag,
the device drops ‘select response,’ ‘condition code in,’ and ‘data bus
in.’
7. The device address bus is deactivated.
Interrupt-service sequence
Device
address
—___
a
bits
>200
ns
Interrupt ¢
Service Strobe S0
active >200 ns <1.5us
/ <50 ns
Strobe (device) 7 Lo |
<1.5 us >100 ns
l
NIT VY -
>0
Select response
Condition code in
and data bus in
Figure 6-5. Interrupt-service sequence timing diagram
6-10 GA34-0033