IBM 1 Series - Reset Sequences Description; Design Considerations for Operational Sequences

Reset Sequences Description
1. The effect that ‘halt or MCHK,’ ‘system reset,’ or ‘power-on reset’
must have has been discussed throughout this chapter.
2. The ‘halt or MCHK’ and ‘system reset’ tags, when occurring, are
active
for 4.8 microseconds, minimum, as seen at the device interface.
Power-on reset sequencing is discussed in ‘“‘Processor I/O Channel
Electrical Characteristics” in this chapter.
3. The deactivation of the device interface signals that are active at the
time of the reset must be performed within 200 nanoseconds, as seen
at the device interface. The prepare field and I-bit must be reset under
the envelope of a ‘system reset.’
4. The processors may have unpredictable values on the address, data,
and status buses during resets. Therefore, resetting of registers must
not depend on the values of these buses.
5. For specific information concerning a reset sequence in conjunction
with another sequence, refer to the description of the basic sequences
in “Operational Sequences On the Channel”’ in this chapter.
Design Considerations for Operational Sequences
This section highlights some aspects of device-adapter design that require
further explanation. In some cases, typical circuits are used as a vehicle to
explain the aspect under discussion. The area of logic represented should
not be taken in the context of a total design, when other considerations
would result in added function to a logic area. These logic diagrams are
intended only to aid in explanation of channel interface function. Timing
relationships may not be inferred from the logic diagrams; all timing must
be as shown in the timing diagrams. For example, the figures assume one
device only, although an attachment may service more than one device.
The logic figures (Figures 2-16 through 2-19) use the following
conventions:
e Connections—those with a circled “‘I’’ indicate a unit load or drive to
the device interface with the channel; Those with a circled ‘‘J”’
indicate a jumper connection. Circled dots indicate that the signal is
connected to another figure in this subsection. Dots alone indicate that
the signal is used or originates elsewhere in an attachment, but is not
connected to another figure.
e Logic—wedges indicate negative active signals. Logic blocks are
labeled with a particular logic function; the blocks perform that
particular logic function with the polarity of the inputs as shown for
the block. Except for the invert function, logic functions are
considered to produce a positive output internal to a block. In some
cases, a logic function is combined with a signal inversion to indicate
the complete function of the block.
e Labels—signal lines are labeled with the polarity appropriate to the
active level of the signal.
Processor I/O Channel 2-39