IBM 1 Series - Relationship to Other Features; Application Summary

The timer feature is addressed with the seven most-significant bits of the
device address field in the IDCB. The least-significant bit selects one of
the two timers within the attachment for all commands (except Prepare,
where it is ignored). By convention, when the least-significant bit is 0,
timer O is selected; when the least-significant bit is 1, timer 1 is selected.
The seven most-significant bits of the address are changeable by jumper
on the card; the least-significant bit is not changeable.
The timer feature is a DPC device and has no cycle-steal or IPL
capabilities.
The timer feature is connected to the processor I/O channel through the
following buses, as described in detail in Chapter 2:
e Data bus—16 bits wide, bidirectional, with parity checking and
generating (odd parity per byte).
e Address bus—17 bits wide (0-16), receiving only; bit 16 is used to
denote a DPC device command and to gate receivers active.
e Request in bus—16 bits wide, driving only.
Relationship to Other Features
The timer card is plugged into any I/O position of an IBM 4955 or 4953
Processor or any position of an I/O expansion unit. There is no limit to
the number of timer cards that can be used in a system.
There is an optional filtering capability of the customer digital input lines
brought into the timer card. This option is selected with jumper wires on
the component side of the timer card either for TTL input or filtered TTL
input. The location of the jumper wires is illustrated in Figures 3-2 and
3-3.
Application Summary
The following paragraphs describe the use of the timer feature. The X
appearing after the word “‘timer’’ denotes either timer O or timer 1.
High Accuracy or Nonstandard Frequency Counting
To utilize a clock of any arbitrary accuracy or frequency up to 1MHz, the
‘timer X customer clock’ input should be used, and the timer mode
controls should be set to select the customer time base.
Timer Feature 3-3