IBM 1 Series - Digital Input Operation

Digital Input Operation
Each DI group can operate in one of four modes: (1) non-interrupting, (2)
process interrupt, (3) external sync, and (4) diagnostic.
Non-Interrupting Mode
When operated in the non-interrupting mode, the state of the DI group
non-latching input register is read with the Read PI command. This
command reads the history of the DI inputs from the latching PI register.
The PI register records the first logical 0 to logical 1 transition of each DI
input following any system or feature reset. The Read PI With Reset
command reads the latching PI register and then resets it at the end of the
instruction cycle.
Process Interrupt Mode
The process interrupt mode is entered by performing the Arm PI
command. The first logical 0 to logical 1 transition on any input of the
armed group sets the appropriate bit in the latching register and causes an
interrupt to be posted to the channel. After the interrupt is serviced, a
Read PI With Reset command reads the latching register and resets it,
allowing a new interrupt to be generated on the next transition of any
input point of that group. If the interrupt is serviced and a Read PI
command is issued, the PI register is not reset and a new interrupt is not
generated.
External Sync Mode
Figure 5-3 is a timing diagram for DI external sync. This sequence is
executed as follows:
1. The external sync mode is entered by performing the Arm External
Sync command. This causes the ‘ready’ output line to become active,
indicating that the system is ready for new input data.
2. A subsequent logical 0 to logical 1 transition on ‘external sync’ by the
user’s equipment latches the group register, deactivates the ‘ready’ line,
and posts an interrupt to the channel.
3. After the interrupt is serviced, a Read DI command reads the DI
register, resets the register, and activates the ‘ready’ line.
Program control Program control
ti a a a
Prepare Arm Service Read with reset
L
Ready | | C-
| |
External | | <lus | <1 us
sync | {
| |
|
YY
Ye
Interrupt | | Pe
Figure 5-3. DI external sync timing diagram
5-6 GA34-0033