IBM 1 Series - Cycle-Steal Service Sequence Description

Cycle-Steal Service Sequence Description
2-24
GA34-0033
Refer to Figure 2-10. Cycle-steal input and output sequences are executed
as follows:
1.
‘Service gate’ is activated. The device detecting the first leading edge
of the ‘service gate’ activation following a poll capture is the selected
device for the cycle-steal service sequence. This is called service gate
capture.
Upon service gate capture, the device activates the ‘address bus’ and,
if a byte transfer is to take place, ‘cycle byte indicator.’ If the
sequence is an input transfer, “data bus’ and ‘cycle input indicator’ are
also activated. These signals must be activated prior to the activation
of ‘service gate return,’ and they must be held valid and must not
change value until the deactivation of ‘service gate’ and ‘data strobe,’
as measured at the device interface.
The permissible delay, T2, from ‘service gate’ to ‘service gate return,’
as seen at the device interface, is 3 microseconds, maximum. There is
no specific time-out on this delay. The delay is provided for
convenience only; however, for performance reasons, this delay should
be held to a minimum.
‘Status bus’ (and ‘data bus’ on output sequences) is activated by the
channel.
‘Data strobe’ is activated. The duration of ‘data strobe,’ CT3, is 200
nanoseconds, minimum, as seen at the device interface.
As denoted by the relationship of, CT1 and CT2 in Figure 2-10,
‘status bus’ and ‘data bus’ may be valid only just prior to the
activation of ‘data strobe’ at the device interface; therefore,
registration of status and data with the leading edge of ‘data strobe’ is
not recommended unless delays are built into the attachment to allow
for trigger conditioning. Because parity must be checked by the device
on output sequences, and error status may be posted to the device on
‘status bus,’ registration of data during ‘data strobe’ may necessitate
double buffering.
If an error is posted to the device on ‘status bus’ in a burst-mode
transfer (not the last transfer), the device must complete one more
service sequence. This additional transfer is a dummy cycle. No
device-held parameters are to be updated nor are any additional status
bus bits to be accumulated.
‘Service gate’ and ‘data strobe’ are deactivated simultaneously at the
processor channel output. As denoted by the relationship of CT3 and
CT4 in Figure 2-10, ‘data strobe’ may extend beyond the active
envelope of ‘service gate’ by 100 nanoseconds, maximum, but the
overlap of ‘data strobe’ and ‘service gate’ is 100 nanoseconds,
minimum, as seen at the device interface.