IBM 1 Series - Page 36

jouuryD
O/]
JOsssd01d
SCC
Channel time-out
crs
Service gate
Y
)
Tl
Address bus bits 0—15
—
a
sa
——_
—
=
Condition code in
\
i
bus (address key) | | |
Cycle byte indicator
Cycle input indicator
crs 7
|
|
(input) |
j t
' |
Data bus (input) \ | |
LVS | LIS |
T2
|
Service gate return :
| T4
Status bus ! N\A]
I i
| CT2 |
Data bus (output) 7
LVS
| CT3
CT1 _ _
Data
strobe
>
>
Key:
Timines: CYT =channel times.
snINgS. T = attachment-controlled times.
0<T1<T2 <3 us LVS. = last valid signal, occurring in time, of a group of
0<T3<T4<3 us signals being activated on the channel. The group
100 ns <CT1 is shown linked by short, dotted lines on the timing
0<CT2 <CT1 diagram.
200 ns < CT3 LIS == last invalid signal, occurring in time, of a group of
100 ns < CT4 < CT3 + 100 ns signals being deactivated on the channel. The group
0 <CTS (burst only) is shown linked by short, dotted lines on the timing
diagram.
Figure 2-10. Cycle-steal service sequence timing diagram