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IBM 1 Series - Chapter 6. Customer Direct Program Control (DPC) Adapter Feature; Introduction; Relationship to Other Features

IBM 1 Series
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Chapter
6.
Customer
Direct
Program
Control
(DPC)
Adapter
Feature
Introduction
Relationship
to
Other
Features
Figure
6-1
is
a
block
diagram
of
the
customer
DPC
adapter
feature,
which
provides
the
end-user
with
a
subset
of
the
processor
I/O
channel.
The
interface
adheres
to
the
processor
I/O
channel
architecture,
with
an
additional
throughput
delay
of
approximately
2.5
microseconds.
The
DPC
adapter
feature
is
designed
to
perform
direct
program
control
(DPC)
functions
only
and
can
be
configured
to
accommodate
4,
8,
or
16
I/O
device
addresses;
therefore,
the
feature
allows
interrupt
vectoring
for
up
to
16
interrupting
sources.
The
actual
number
of
devices
connected,
when
configured
as
stated
here,
is
limited
by
the
termination
scheme
implemented
by
the
customer.
The
termination
scheme
must
provide
data-buffering
hardware
and
control-handshaking
logic
to
expand
the
number
of
attached
devices
to
the
configured
limits.
The
I/O
device
address
configuration
allows
interrupt
vectoring
for
up
to
16
interrupting
sources
by
individual
device
address.
A
DPC
operation
causes
a
parallel
transfer
of
one
16-bit
word
of
data
or
control
information
to
or
from
an
I/O
device.
An
Operate
I/O
instruction
must
be
executed
for
each
data
transfer.
Data
bus
parity
is
checked.
When
parity
is
not
generated
by
an
I/O
device
on
the
input
data
bus,
internal
circuitry
on
the
feature
card
generates
odd
parity.
All
the devices
attached
to
the
DPC
adapter
share
a
common
prepare
field
(interrupt
level
and
I-bit).
The
adapter
has
75
lines,
including
18
data
bus-out
bits
(with
two
parity
bits),
18
data
bus-in
bits
(with
two
parity
bits),
16
interrupt
request
in
lines
(when
configured
for
16
I/O
device
addresses),
three
function
bits,
four
modifier
bits,
four
I/O
device
address
bits,
and
12
control
and
response
lines.
The
data
flow
is
always
16
bits
without
the
parity
option
or
18
bits
(including
two
parity
bits)
with
the
parity
option.
Diagnostic
capability
is
designed
into
the
DPC
adapter
feature
card.
This
capability
allows
the
user
to
send
data
or
control
information
from
the
processor
and
“‘wrap’”’
the
same
information
back
to
the
processor
from
either
the
adapter
card
or
from
an
external
I/O
device.
The
DPC
adapter
feature
uses
TTL
nonisolated
cable
drivers
with
a
current
capacity
of
175
mA.
This
allows
a
wide
range
of
customer
termination
schemes.
Jumper
pins
are
provided
on
the
circuit
card
to
select
the
address
domain
of
the
adapter.
The
configuration
must
include
assignment
of
a
device
address
with
a
range
of
either
4,
8,
or
16 contiguous
addresses.
A
parity
option
is
also
selected
to
be
compatible
with
attached
devices.
Interrupts
can
be
masked
off
during
external
diagnostic
mode
by
jumper
selection.
Customer
Direct
Program
Control
(DPC)
Adapter
Feature
6-1

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