IBM 1 Series - Processor-Initiated IPL Sequence Description

Processor-Initiated IPL Sequence Description
Refer to Figure 2-14. The processor-initiated IPL sequence is executed as
follows:
1.
The ‘initiate IPL’ line is activated at the processor channel output,
along with status bus bit O or 1, as a result of the operator pressing
the Load key. Status bus bit 0 and 1 reflect the position of the IPL
Source switch (Primary or Alternate), at the time the Load key was
pressed. The first ‘system reset’ in this IPL sequence is also activated
at this time. ‘Initiate IPL’ and the ‘status bus’ are held valid until the
activation of the ‘IPL’ tag at the processor channel input after the first
‘system reset’ is deactivated. (There may be only one primary and one
alternate device on the channel.)
On the activation of the logical AND of ‘initiate IPL’ and ‘system
reset,’ the device must dc-reset the ‘IPL’ tag due to a previous IPL
request within 200 nanoseconds, T1, as seen at the device interface.
On activation of the first ‘system reset,’ the device executes all other
system reset functions. Because of possible skew, ‘system reset’ may
lag ‘initiate IPL’ and the ‘status bus’ at the device interface. Therefore,
the ‘IPL’ tag may temporarily become active at the device interface
prior to the first ‘system reset.’ However, the processor channel
ignores the ‘IPL’ tag during the initial part of the sequence and does
not examine the tag line until the first ‘system reset’ has been
activated.
In no case should the selected IPL device use the leading-edge
transition of the first ‘system reset.’ This is because the first ‘system
reset’ could also lead the ‘initiate IPL’ and ‘status bus’ at the device
interface.
The first ‘system reset’ is deactivated after a time, CT1, of 4.8
microseconds, minimum, at the device interface. The IPL source device
then activates the ‘IPL’ tag. The attachment must not use the trailing
edge transition of the first ‘system reset’ to activate the ‘IPL’ tag;
rather, the attachment should use a dc-set condition of the ‘initiate
IPL’ tag, the particular status bus bit, and the absence of the first
“system reset’ to activate the ‘IPL’ tag. The time, T2, from the
deactivation of the first ‘system reset’ to the activation of the ‘IPL’ tag
must be greater than O, as seen at the device interface, but the
maximum time is device-dependent. This maximum time should be
kept within reasonable limits and, generally, this time should only
depend upon electronic, rather than mechanical delays.
As a result of ‘IPL’ going active, ‘initiate IPL’ is deactivated. The
‘status bus’ is not valid for the primary/alternate selection portion of
the IPL sequence after the time when ‘initiate IPL’ is deactivated.
A second ‘system reset’ is activated. The time from the deactivation of
‘initiate IPL’ and activation of the second ‘system reset,’ CT3, is 200
nanoseconds, minimum, as seen at the device interface. This second
‘system reset’ is unique. The IPL source device maintains an active
‘IPL’ tag while using this ‘system reset’ to enable the cycle-steal
transfer for the storage load. The device should use only the trailing
edge of the second ‘system reset’ to accomplish this enabling.
Processor I/O Channel 2-33