IBM 1 Series - Service Group Line Definitions

Service Group Line Definitions
Address Bus Bits 0-15. This is a 16-bit bidirectional bus that is received
by all I/O devices. The bus is used on direct program control (DPC)
sequences to select and pass commands to the I/O devices. On DPC
sequences, address bus bits 0-15 are logically equal to the contents of bits
0-15 of the first word of the IDCB. The channel select bit (IDCB bit 0)
on address bus bit 0 can be ignored for device selection.
The address bus is also used on cycle-stealing sequences to present main
storage addresses to the channel controls. On cycle-steal service sequences,
address bits 0-15, which are driven by the I/O device, correspond to
storage address bits O-15 of the data to be transferred.
Address bus bits 0-15 are not used on interrupt-service sequences.
Address Bus Bit 16. This bit is an outbound tag received by all I/O
devices. When active, this tag signals a DPC sequence to the I/O devices.
The receiver for this tag is always enabled.
Data Bus. This is an 18-bit bidirectional bus with 16 bits of data and two
parity bits (odd parity by byte). The data bus transfers data and control
information: (1) between the processor and the I/O devices on DPC and
interrupt-service sequences, and (2) between cycle-stealing devices and
main storage on cycle-steal service sequences.
On DPC write sequences, data bus bits 0-15 are logically equal to the
contents of bits 16—31 (second word) of the IDCB. If a single byte is to
be transferred to the device, the byte is transferred from bits 24-31 of the
IDCB; bits 16—23 should all be 0’s. DPC write sequences are specified by
address bus bit 1 (IDCB bit 1) equal to a logical 1.
Parity is always maintained for both bytes of the data bus on DPC write
sequences; however, certain relaxations of the requirement to check parity
on both bytes are allowed if a DPC device is byte-oriented. A
byte-oriented device is a DPC device that does not use bits 16—23 of the
IDCB for any DPC write or control function as specified in bits 1-3 of the
IDCB. In this case, the device does not need to examine or parity check
data bus bits 0-7 on DPC write or control sequences. A device that uses
bits 16—23 of the IDCB for at least one DPC write sequence is not a
byte-oriented device. Cycle-stealing devices cannot be byte-oriented
devices because they implement the start functions.
On DPC read sequences, data bus bits O0Q—15 are driven by the device, and
correspond to bits 16-31 of the IDCB. If a single byte is to be transferred
from the device, the byte is transferred on data bus bits 8-15 with data
bus bits O—7 equal to logical 0’s. DPC read sequences are specified by
address bus bit 1 (IDCB bit 1) equal to logical 0. Parity must be
maintained on both bytes of the data bus on DPC read sequences.
On interrupt-service sequences, the data bus is used to pass the interrupt ID
word to the processor. Data bus bits 0—15 are driven by the device, and
correspond to bits 0-15 of the interrupt ID word. The first byte of the
interrupt ID word (bits 0—7) is the interrupt information byte; the second
byte (bits 8-15) is the device address of the device being serviced.
Processor I/O Channel 2-7