IBM 1 Series - Page 19

2-8 GA34-0033
Parity must be maintained on both bytes of the data bus on interrupt
service sequences.
On cycle-steal service sequences, the data bus bits have the following
meanings:
e Output, word transfer—data bus bits 0-15 are logically equal to the
contents of the word at the storage address presented by the device;
this storage address must be even. The device indicates an output word
transfer by presenting ‘cycle input indicator’ equal to logical 0 and
‘cycle byte indicator’ equal to logical 0.
e Input, word transfer—data bus bits O—15 are driven by the device and
correspond to the word to be placed at the storage address presented
by the device; this storage address must be even. The device indicates
an input word transfer by presenting ‘cycle input indicator’ equal to
logical 1 and ‘cycle byte indicator’ equal to logical 0.
e Output, byte transfer—the main storage address presented by the
device determines the alignment of the byte on the data bus. If the
storage address is even, data bus bits 0-7 are logically equal to the
contents of the byte at the storage address. If the storage address is
odd, data bus bits 8-15 are logically equal to the contents of the byte
at the storage address. The device indicates an output byte transfer by
presenting ‘cycle input indicator’ equal to logical 0 and ‘cycle byte
indicator’ equal to logical 1.
e Input, byte transfer—the device must align the byte on the data bus
according to the storage address being presented. If the storage
address is even, data bus bits 0-7 are driven by the device and
correspond to the byte to be placed at the storage address. If the
storage address is odd, data bus bits 8—15 are driven by the device and
correspond to the byte to be placed at the storage address. The device
indicates an input by presenting ‘cycle input indicator’ equal to logical
1 and ‘cycle byte indicator’ equal to logical 1.
The I/O architecture allows both byte and word cycle-steal data transfers
during the execution of a given cycle-steal operation. For example, an
operation transferring an even number of bytes into a data table on an odd
storage boundary could transfer one byte, then a number of words, and
then end with a byte transfer.
Parity is maintained on both bytes of the data bus during cycle-steal
output transfers. I/O devices must check both bytes of the data bus
regardless of whether a word or byte is being transferred. Parity must be
maintained on both bytes of the data bus on cycle-steal input transfers.
During byte transfers, the channel or device must maintain a stable data
bus and parity for purposes of parity checking by the receiver of the data.
However, the logical value of the particular byte not being used does not
have to be specified because it is parity checked only. For output byte
transfers, the value of the unused byte may be different on each transfer
and may be different among the Series/1 processors. For input byte
transfers, most device attachments, as a matter of practice, have found it
simplest to zero out the unused byte and force the parity bit accordingly.