IBM 1 Series - Poll Sequence Description

Poll Sequence Description
Refer to Figures 2-11, 2-12, and 2-13. The poll sequences with ‘poll
return’ or ‘burst return’ are executed as follows:
1.
When the device detects an external interrupting condition, it activates
the appropriate bit of the ‘request in bus,’ as determined by the level
field and the I-bit of the Prepare command. The device may activate
an interrupt request on the interface only while its I-bit (device mask)
is on (equal to a logical 1).
Once the appropriate bit of the ‘request in bus’ is activated, that bit
must remain active until the device has captured a poll, executed a
Prepare command to set the device I-bit off, or received: a Device
Reset, ‘halt or MCHK,’ ‘system reset,’ or ‘power on reset.’ If an I/O
device has an interrupt request active and executes a Device Reset or
Prepare command, the device, as appropriate, drops its request or
alters its requested level prior to the deactivation of ‘data strobe,’ as
seen at the device interface.
When the device requires an access to storage, it activates the ‘cycle
steal request in’ line. Once ‘cycle steal request in’ has been activated,
the line must remain active until the device has captured a poll, or has
received a ‘halt or MCHK,.’ ‘system reset,’ or ‘power on reset.’ If the
device has already activated a cycle-steal request on the interface and
detects a device-directed reset, the device must complete the servicing
for that cycle-steal request. This servicing is a dummy transfer and is
to be an output transfer (read from storage). In the case of burst
mode, the dummy transfer must appear as the last transfer of the burst
mode. Because the channel is unaware that these are dummy transfers,
no device-held parameters are to be updated nor are any status
conditions to be recorded or reported by the device.
‘Poll [D’ is activated by the channel, either as a result of the particular
device’s request or from other requests previously presented to the
channel. ‘Poll ID’ and a subsequent poll can occur completely
asynchronous to the device’s request. When the device detects
activation of the ‘poll ID’ bits matching the type of request the device
has activated (interrupt level or cycle-steal, regardless of whether or
not the device has activated the request on the ‘request-in’ bus), the
device must not allow its state of request to further influence the
decision to capture or propagate the ‘poll’ tag. A time, T1 (measured
at the device interface), of 100 nanoseconds after the activation of
‘poll ID’ and prior to the device request becoming active, on the
request in bus is the latest time in which a device may delay the
decision to capture or propagate.
‘Poll’ is activated. The time, CT1, from the activation of the ‘poll
identifier’ to the activation of ‘poll,’ is 180 nanoseconds, minimum, as
measured at the processor channel input. The device interface will see
the poll tag delayed from the poll identifier tag by 180 nanoseconds
plus the delay at each device propagating the poll. ‘Poll’ is held valid
by the processor channel interface until the activation of ‘poll return’
or ‘burst return’ at the processor channel input. When the device
detects the leading edge of ‘poll,’ the device must take action to either
capture or propagate the poll.
Processor I/O Channel 2-27