IBM 1 Series - Page 17

Cycle-Steal/IPL Subset
The cycle-steal/IPL subset consists of control buses and tags to support
cycle-steal, burst transfer, and IPL operations. This subset provides the
means to present cycle-steal requests to the processor, to resolve
contention, and to service the cycle-steal transfers. The cycle-steal/IPL
subset, in conjunction with the basic and the interrupt subsets, supports
devices that cycle-steal and DPC devices capable of IPL. The I/O signal
lines in the cycle-steal/IPL subset are shown in Figure 2-5.
Service group signal lines
Signal Number
name Direction of lines
Address bus bits 0-15 (Note 1) Ge | 6
Cycle input indicator (————— |
Cycle byte indicator S|
Status bus mente
Initiate IPL (Note 2) ——cn |
IPL (Note 2) S|
Poll group signal lines
Signal Number
name Direction of lines
Cycle steal request in |
Burst return (Note 3) —— |
Notes:
1. Address bits 0-15 must have full bidirectional capability for this subset.
2. Required only for devices supporting IPL. Initiate IPL is not required for devices
that only support IPL from a host system.
3. Required only if burst cycle-steal transfers are supported by the device.
Figure 2-5. Cycle-steal/IPL subset
2-6 GA34-0033