IBM 1 Series - Page 45

2-34
GA34-0033
The time from the activation of the ‘IPL’ tag by the device to the
activation of the second ‘system reset’ by the processor channel, CT4, is
less than 500 microseconds. This time may be used by a host processor
initiating an IPL sequence as a time-out to detect a defective IPL
sequence.
5.
The second ‘system reset’ is deactivated. IPL cycle-steal requests and
transfers may then begin. The time, T3, from the deactivation of the
second ‘system reset’ to the activation of the first cycle-steal request,
must be greater than O, as seen at the device interface. The maximum
time is device-dependent; however, this time should be kept to a
minimum. At this time, the status bus returns to its original function;
that is, the reporting of status information to the I/O device being
serviced. The IPL record length can be up to a maximum of 64K
bytes. Successful completion of IPL is signaled to the processor by the
device dropping the ‘IPL’ tag. Time T4, from the end of cycle-steal
requests and transfers (as defined by the deactivation of the last
‘service gate return’) to the deactivation of the ‘IPL’ tag, has a
minimum time of 0. The maximum time is device-dependent, but
should also be kept to a minimum for the same reason as stated for
time T3.
Following the successful completion of IPL and the dropping of the
‘IPL’ tag, the I/O device must be prepared to level 0 with its I-bit on
and presenting an interrupt request to the processor I/O channel. The
device must be available in all other respects. When the interrupt is
accepted, the device presents the device-end interrupt condition code.
If a system reset occurs after the device has enabled cycle-steal
requests and transfers, the device must deactivate the ‘IPL’ tag within
200 nanoseconds at the device interface, terminate the cycle-steal
transfers, and execute all other system-reset functions. Note that this
system reset could be the result of (1) the operator pressing the Reset
key or (2) the operator pressing the Load key to begin another
processor-initiated IPL sequence where ‘system reset’ leads the ‘initiate
IPL’ tag at the device interface. Therefore, this represents an added
condition for resetting the ‘IPL’ tag. Note also that this condition is
dependent upon being in an enabled state for IPL transfer as a result
of the second ‘system reset.’
If, during cycle-steal transfers, an error condition is posted to the
device on the status bus, the device must terminate further requests
and cycle-steal transfers, leave the ‘IPL tag’ active, and not present an
end interrupt. If, during the cycle-steal requests and transfers, a
hardware failure causes a channel time-out, the system remains in a
‘“‘hung’’ condition; the device should leave the ‘IPL’ tag active. ‘Halt or
MCHK’ does not occur so that diagnosis of the problem in the state in
which the failure or error occurred is allowed.
Attachment methods for devices with power supplies external to a
processor or I/O expansion card file must be capable of executing an
IPL if the device is powered up to a ready condition either before or
after the processor has activated the ‘initiate IPL’ tag, ‘status bus,’ and
the first ‘system reset’ of a processor-initiated IPL sequence.