IBM 1 Series - Page 46

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O/]
JOSsed01d
Se-C
Initiate IPL \
Status bus bit 0 or 1
l CT2
a
System
reset
CT1
\
LVS/\T1 T2
—_ +
IPL |
IPL cycle-steal requests and transfers
ee
*IPL tag from previous IPL request
Timings.
T1 < 200 ns
T2 >0
T3 > 0
T4>0
CT1 > 4.8 us
CT2 >0
CT3 > 200 ns
CT4 < 500 us
Figure 2-14. Processor-initiated IPL sequence timing diagram
> .
Normal cycle-steal usage
CT3
am
ae
SC
USE
|
q
x
CT1
“DS
{
{
\ ( (
))
Crs T3 T4
( (
))
Key:
CT = channel times.
T = attachment-controlled times.
LVS last valid signal, occurring in time, of a group of
signals being activated on the channel. The group
is shown linked by short, dotted lines on the
timing diagram.