IBM 1 Series - Page 51

Tags and Data Strobe
“Operational Sequences on the Channel” in this chapter specified that for
DPC, interrupt-service, and cycle-steal service sequences, the deactivation
of a return tag (‘address gate return’ or ‘service gate return’) occurred only
after the deactivation of the respective outgoing tag (‘address gate’ or
‘service gate’) and ‘data strobe.’
Because the channel deactivates the outgoing tag simultaneously with the
deactivation of ‘data strobe,’ the phase relationships between the outgoing
tag and ‘data strobe’ could be skewed at the device interface. At the
device interface, ‘data strobe’ can be deactivated either before or after the
deactivation of the outgoing tag. However, ‘data strobe’ would never be
active completely outside the active envelope of the outgoing tag for that
operational sequence. This suggests that a method for keeping the return
tag active to meet the condition specified in the first paragraph is to
logically OR the outbound tag with ‘data strobe.’ This is true, provided
that certain considerations are taken into account. First, as seen by any
device, ‘data strobe’ or ‘address gate’ can occur randomly outside of a
DPC sequence, when ‘address bus bit 16’ (DPC sequence) is not active.
This is because of the presence of main storage physically attached to the
channel for the 4952 and 4953 processors. Second, as seen by the poll
mechanism of any device, ‘data strobe’ can occur randomly. This is
because of the asynchronous nature of polling and service sequences on
the channel. A device may operate its poll mechanism while it or other
devices are executing a sequence associated with the service group. These
two considerations make it necessary to (1) ensure that the logical OR is
gated only for those sequences specifically of interest to the device when it
is selected, and (2) keep the poll mechanism operation independent of
‘data strobe.’
Figure 2-16 illustrates a method for keeping the return tags active for
DPC, interrupt, and cycle-steal sequences. For a DPC sequence, DPC
selection is the condition of system ready, ‘address bus bit 16’ active, and
a true device address compare @. The logical OR of ‘address gate’ and
‘data strobe,’ @ gated with DPC selection @ @ will give the maximum
‘+address gate’ envelope, correcting for any outgoing tag skew. For
interrupt and cycle-steal service sequences, device selection is based on the
first active ‘service gate’ following a poll capture.
2-40 GA34-0033