IBM 1 Series - Page 142

DI External Sync
Process Interrupt (PI)
Each position of the PI data register records, with a 1-bit, the first O-bit to
1-bit transition on the corresponding user-input point. The data in the
register remains until it is reset by one of the following:
e Read PI With Reset command
e Arm PI command
e Device Reset command
e System reset
e Power-on reset
When a bit in the PI data register becomes active, a process interrupt is
generated if PI mode was previously set with an Arm PI command. For
additional information, see ‘“‘Process Interrupt Mode”’ under “Digital Input
Operation”’ in this chapter.
A DI/PI group can be tested using two special commands: Set Test Ones
and Set Test Zeros. When the appropriate command is executed, the user
inputs and outputs are disabled, either 1’s or 0’s are placed on the input
receivers, and the external sync receiver is pulsed. Then, when subsequent
Read commands are issued, the group responds exactly as if the actual
user inputs, including the PI and external sync functions, had been set.
DI external sync consists of two signal lines: an ‘external sync’ input line
and a ‘ready’ output line. A DI group is set to external sync mode by
execution of the Arm DI External Sync command. When external sync
mode is armed and the system is ready for more DI data, the ‘ready’ line
from the DI group is set active. The user places data on the input points,
and then activates the ‘external sync’ line. When ‘external sync’ becomes
active, the data in the DI data register is assumed to be good and the
contents of the register are held. An interrupt is then posted; the ‘ready’
line becomes inactive and stays inactive until the appropriate command,
normally Read DI, is executed. The ‘external sync’ line must then perform
another transition from the O to the 1 state to cause another interrupt.
External sync mode is reset by an Arm PI command, a Device Reset
command, a Halt I/O command, or any reset condition.
A digital input group is set to PI mode by the Arm PI command. The
process interrupt function is performed by logically ORing the bits in the
PI data register of the DI group. Any PI register bit that becomes active
generates an interrupt.
PI mode is reset by an Arm External Sync command, a Device Reset
command, a Halt I/O command, or any reset condition.
Integrated Digital Input/Output Feature 5-3