IBM 1 Series - Page 191

solid state
switch 4-27
switch/TTL 4-27
status
after power transitions 3-9
after resets 3-9
bus 2-10
strobe
data (I/O channel line) 2-10
DPC adapter line 6-5
subsets of processor I/O channel signal lines
basic 2-4
cycle-steal/IPL 2-6
interrupt 2-5
switching characteristics and voltage levels 2-61
system-related characteristics 4-21
system reset
DPC adapter line 6-7
I/O channel line 2-11
tags and data strobe 2-40
TCC/CAP connections
DPC adapter feature 6-17
integrated digital I/O feature
input group 0 5-13
input group 1 5-14
output group 2 5-15
output group 3 5-16
timer feature 3-11
teletypewriter adapter feature 1-2, 4-1
applications 4-5
bit rates 4-3
cable connection 4-30
communications lines 4-22
customer access panel connections 4-33
data transfer 4-3
data transmission 4-11
design considerations 4-3
cable connection 4-3
device information 4-30
device information 4-30
driver/receiver information 4-26
electrical characteristics 4-22
bit-rate selection 4-25
cable length 4-24
communication lines 4-22
driver/receiver information 4-26
input circuits description 4-22
jumper selections 4-24
output circuits description 4-23
power supplies 4-28
initial program load 4-12
operational characteristics 4-12
commands for receive/transmit operations 4-15
error recovery 4-2]
interrupt presentation 4-14
power failure 4-21
read control 4-20
receive operations 4-13, 4-17
transmit operations 4-16
write control 4-21
optimum interface selection 4-6, 4-10
X-6 GA34-0033
teletypewriter adapter feature (continued)
options
input 4-1, 4-5
output 4-1, 4-5
physical characteristics 4-29
components description (I/O channel) 2-70
signal pin assignments 4-29
timer, interval 3-7
timer card
cable connectors 3-11
driver/receiver circuits 3-4
jumper selections 3-5
timer feature 1-2, 3-1
addressing 3-3
application
event counting 3-6
high-accuracy counting 3-3
nonstandard frequency counting 3-3
pulse counting 3-6, 3-8
pulse duration counting 3-6, 3-8
sequence 3-7
design considerations 3-12
drivers 3-10
electrical characteristics 3-10
drivers 3-10
receivers 3-10
interrupts 3-8
operational! characteristics 3-8
interrupt presentation 3-9
interrupts reported at interrupt time 3-8
status after power transition and resets 3-9
physical characteristics 3-11
CAP connections 3-12
jumper selections 3-12
signal pin assignments 3-11]
receivers 3-10
running modes 3-1]
signal lines 3-6
considerations 3-7, 3-12
customer clock 3-8
external gate 3-8
external gate enable 3-8
run state 3-8
wiring practices 3-12
timing diagram
cycle-steal service sequence 2-25
DI external sync 5-5
DO external sync 5-6
DPC sequence 2-2]
host-initiated IPL sequence 2-37
input, DPC adapter 6-7
interrupt service, DPC adapter 6-10
interrupt-service sequence 2-23
output, DPC adapter 6-6
poll
propagate 2-32
sequence with burst return 2-31
sequence with poll return 2-30
processor-initiated IPL sequence 2-35
receive operations 4-18
transmit operation 4-16
top-card connector (TCC) (see also TCC/CAP connections)
pin assignments (timer features) 3-11