IBM 1 Series - Page 28

For example, assume that a processor interrupt poll request becomes active
and is gated into the ‘“‘poll for interrupt’ block. This starts the polling
sequence. When the poll for interrupt sequence is complete, the poll group
resource is waiting for the service group. When the service group beocmes
available, the interrupt acceptance block is gated, thus tying up the service
group. However, as soon as the interrupt acceptance block is gated, the
poll group is free to do further polling concurrent with the service group.
As another example, assume that the cycle-steal burst sequence is active.
Figure 2-7 shows that this sequence degates all other sequences. Note also
that the last sequence of a burst operation enables concurrent polling.
Each major sequence is described in subsequent sections. Timing diagrams
are used to show the important timing relationships that the designer needs
to adhere to (or be aware of) when designing an I/O attachment for the
I/O channel.
The designer has no control over, but must be aware of, channel times
(CT). The designer does have contro] of the attachment-controlled times
(T-times), because these are considered dependent times.
The diagrams use the convention of an up level to denote an active tag or
a valid bus value.
The designer should ensure that the signals presented to the I/O channel
meet the specified T-times, as shown on the timing diagrams. Because the
designer does not control the loading, as seen at the output of the
interface drivers in a given configuration, these timings should be met,
assuming the maximum loading permissible for the particular drivers being
used. There are cases where differences in driver delays must be
considered. For example, certain signals must be deactivated prior to a tag
being dropped at the device adapter interface. In such cases, one driver
can be considered at nominal delay and the other at worst-case delay, with
both at maximum load.
Processor I/O Channel 2-17