IBM 1 Series - Page 78

Each cable carries twenty signal lines, which are arranged so that cable #1
plugs into the top of the A-socket and cable #4 plugs into the bottom of
the A-socket.
I/O channel
I/O pin cable assignment
Line name Direction assignment #1 #2 #3 #4
Address bus bit 0 ————p> BY B02
Address bus bit 1 en BO3 BO3
Address bus bit 2 <fe B04 B04
Address bus bit 3 Gp B05 BOS
Address bus bit 4 ——— BO7 BO7
Address bus bit 5 <——p- B08 B08
Address bus bit 6 B09 BO9
Address bus bit 7 B10 B10
Address bus bit 8 B12 B12
Address bus bit 9 D02 DO02
Address bus bit 10 ——» D4 ~D04
Address bus bit 11 fe DO5 DO05
Address bus bit 12 Gon D06 D06
Address bus bit 13 ——— —/:1D07 D07
Address bus bit 14 ——- Do9 DO9
Address bus bit 15 Sa D10 D10
Address bus bit 16 sooner D11 D1i1
Address gate os M08 B08
Address gate return <Gmemme (V{()9 B09
Burst return Gee P14 D04
Condition code in bitO <= Di12 D1i2
Condition code in bit 1 G——e—= |) 13 D13
Condition code in bit2 «== B13 B13
Cycle byte indicator Ge P 1 ) D10
Cycle input indicator Gee =—P) DO9
Cycle steal request in Gomes V2 B02
Data bus bit 0 ~—— G02 BO2
Data bus bit 1 ——= G03 B03
Data bus bit 2 —_—— G04 B04
Data bus bit 3 ——— G05 BOS
Data bus bit 4 fee G07 B07
Data bus bit 5 Go G08 B08
Data bus bit 6 — G09 BO9
Data bus bit 7 Se G10 B10
Data bus bit PO —— G12 B12
Data bus bit 8 ——— J02 D02
Data bus bit 9 G—p 04 D04
Data bus bit 10 —— js D05
Data bus bit 11 Gp JG D06
Data bus bit 12 — JO7 D07
Data bus bit 13 — 09 DO9
Data bus bit 14 <——— Ji0 D10
Data bus bit 15 ——— 11 Dil
Data bus bit Pl Ge 1 D12
Figure 2-28 (Part 1 of 2). I/O channel pin and cable assignments—signal lines
Processor I/O Channel 2-67