30
INOVANCE TECHNOLGY EUROPE GmbH
SV660N Startup Procedure_EN_v1.4_20220826.docx
Example 1: This trace show the value of [49] “SYNC and IRQ phase position” when the jitter from EtherCAT
master is acceptable. The EtherCAT master cycle time is 4 ms.
Example 2: This trace show the value of [49] “SYNC and IRQ phase position” when the jitter from EtherCAT
master is NOT acceptable. The EtherCAT master cycle time is 4 ms. In this case it can observe that in some
cycles the [49] value is too high. This is because EtherCAT SYNC signal is very close to Master IRQ interruption
and these two signals are overlapping. In this example, the "Time Shift" parameter of the master has been
modified from 12% to 30% to cause this effect
To Next Page
Loading...
