Functional Architecture Overview Intel® Server Board S2600CO Family TPS
22 Revision 1.0
Intel order number G42278-002
o Demand and Patrol Scrubbing
o DRAM Single Device Data Correction (SDDC) for any single x4 or x8 DRAM
device. Independent channel mode supports x4 SDDC. x8 SDDC requires
lockstep mode
o Lockstep mode where channels 0 and 1 and channels 2 and 3 are operated in
lockstep mode
o Data scrambling with address to ease detection of write errors to an incorrect
address.
o Error reporting by the Machine Check Architecture
o Read Retry during CRC error handling checks by IMC
o Channel mirroring within a socket
CPU1 Channel Mirror Pairs (A,B) and (C,D)
CPU2 Channel Mirror Pairs (E,F) and (G,H)
o Error Containment Recovery
Improved Thermal Throttling with dynamic Closed Loop Thermal Throttling (CLTT)
Memory thermal monitoring support for DIMM temperature
3.2.2.1 Supported Memory
Table 3. UDIMM Support Guidelines
Ranks Per DIMM
and Data Width
Memory Capacity Per DIMM
1
Speed (MT/s) and Voltage Validated by
Slot per Channel (SPC) and DIMM Per Channel (DPC)
Table 4. RDIMM Support Guidelines
Ranks Per DIMM
and Data Width
Memory Capacity Per
DIMM
1
Speed (MT/s) and Voltage Validated by
Slot per Channel (SPC) and DIMM Per Channel (DPC)
2
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