Intel Xeon Datasheet

Intel® Xeon™ Processor with 800 MHz System Bus
14 Datasheet
2.3 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking
BCLK[1:0] directly controls the front side bus interface speed as well as the core frequency of the
processor. As in previous processor generations, the Intel® Xeon™ processor with 800 MHz
system bus core frequency is a multiple of the BCLK[1:0] frequency. The processor bus ratio
multiplier will be set during manufacturing. The default setting will be the maximum speed for the
processor. It will be possible to override this setting using software. This will permit operation at a
speed lower than the processor’s tested frequency.
The BCLK[1:0] inputs directly control the operating speed of the front side bus interface. The
processor core frequency is configured during reset by using values stored internally during
manufacturing. The stored value sets the highest bus fraction at which the particular processor can
operate. If lower speeds are desired, the appropriate ratio can be configured by setting bits [15:8] of
the IA-32_FLEX_BRVID_SEL MSR.
Clock multiplying within the processor is provided by the internal phase locked loop (PLL), which
requires a constant frequency BCLK[1:0] input, with exceptions for spread spectrum clocking. The
Intel® Xeon™ processor with 800 MHz system bus uses differential clocks. Details regarding
BCLK[1:0] driver specifications are provided in the CK409 Clock Synthesizer/Driver Design
Guidelines or CK409B Clock Synthesizer/Driver Design Guidelines. Table 2 contains core
frequency to front side bus multipliers and their corresponding core frequencies.
NOTE:
1. Individual processors operate only at or below the frequency marked on the package.
2.3.1 Front Side Bus Frequency Select Signals (BSEL[1:0])
Upon power up, the front side bus frequency is set to the maximum supported by the individual
processor. BSEL[1:0] are open-drain outputs, which must be pulled up to V
TT
, and are used to
select the front side bus frequency. Please refer to Table 12 for DC specifications. Table 3 defines
the possible combinations of the signals and the frequency associated with each combination. The
frequency is determined by the processor(s), chipset, and clock synthesizer. All front side bus
agents must operate at the same core and front side bus frequencies. Individual processors will only
operate at their specified front side bus clock frequency.
Table 2. Core Frequency to Front Side Bus Multiplier Configuration
Core Frequency to
Front Side Bus Multiplier
Core Frequency with
200 MHz Front Side Bus Clock
Notes
1/14 2.80 GHz 1
1/15 3 GHz 1
1/16 3.20 GHz 1
1/17 3.40 GHz 1
1/18 3.60 GHz 1
Table 3. BSEL[1:0] Frequency Table
BSEL1 BSEL0 Bus Clock Frequency
00 Reserved
01 Reserved
1 0 200 MHz
11 Reserved

Intel Xeon Specifications

General

Brand	Intel
Model	Xeon
Category	Processor
Language	English