Intel Xeon - User Manual

Intel
®
Xeon™ Processor with
512 KB L2 Cache and Intel
®
E7500 Chipset Platform
Design Guide
March 2002
Document Number: 298649-002

Intel Xeon Specifications

General

Brand	Intel
Model	Xeon
Category	Processor
Language	English

Summary

1 Introduction

1.1 Reference Documentation

Lists documents relevant to the design guide, providing context for further reading.

1.2 Conventions and Terminology

Defines terms and conventions used throughout the design guide for clear understanding.

1.3 System Overview

Describes the E7500 chipset, its components, architecture, and performance features.

4 Platform Clock Routing Guidelines

4.1 Clock Groups

Defines clock groups and their associated receivers for system clocks.

4.2 Clock Driver Decoupling

Specifies decoupling capacitor requirements for the CK408B clock synthesizer.

4.3 Clock Driver Power Delivery

Provides guidelines for delivering a quiet VDDA supply to the clock driver.

4.4 EMI Constraints

Recommendations for reducing EMI emissions related to clock signals.

5 System Bus Routing Guidelines

5.1 Routing Guidelines for the AGTL+ Source Synchronous 2 X and 4 X Groups

Covers routing guidelines for AGTL+ source synchronous signals.

5.2 Routing Guidelines for Common Clock Signals

Provides guidelines for routing common clock signals on the system bus.

5.3 Routing Guidelines for Asynchronous GTL+ and Miscellaneous Signals

Details routing guidelines for asynchronous GTL+ and miscellaneous signals.

6 Memory Interface Routing Guidelines

6.1 DDR Overview

Provides an overview of DDR memory channels and DIMM population.

6.2 Source Synchronous Signal Group

Details signal grouping for DQ, DQS, and CB, and their associated strobes.

6.3 Command Clock Routing

Guidelines for routing CMDCLK/CMDCLK# pairs to DIMM connectors.

6.4 Source Clocked Signal Group Routing

Provides routing guidelines for source-clocked signals.

7 Hub Interface

7.1 Signal Naming Convention

Defines Hub Interface 2.0 and Hub Interface 1.5 signal naming conventions.

7.2 Hub Interface 2.0 Implementation

Details MCH and P64H2 ballout assignments for simplified hub interface routing.

7.2.1 Hub Interface 2.0 High-Speed Routing Guidelines

Documents routing guidelines for the Hub Interface 2.0 signal groups.

7.2.2 Hub Interface 2.0 GenerationDistribution of Reference Voltages

Explains nominal reference and swing voltage generation for Hub Interface 2.0.

8 Intel 82870 P2 (P64 H2)

8.1 PCIPCI-X Design Guidelines

Covers design guidelines for PCI and PCI-X interfaces.

8.1.1 PCIPCI-X Routing Requirements (No Hot Plug)

Specifies routing requirements for non-hot-plug PCI/PCI-X configurations.

8.1.2 PCIPCI-X Hot Plug Routing Requirements

Details routing requirements for PCI/PCI-X hot plug configurations.

8.2 Hot Plug Implementation

Describes the P64H2's integrated Hot Plug Controllers and their modes of operation.

9 IO Controller Hub

9.1 IDE Interface

Contains guidelines for connecting and routing the ICH3-S IDE interface.

9.1.2 Cable Detection for Ultra ATA66 and Ultra ATA100

Explains how the ICH3-S IDE controller detects cable types for transfer modes.

9.3 PCI

Describes the ICH3-S PCI Bus interface and its implementation.

9.4 USB

Provides guidelines for routing USB signals to minimize signal quality and EMI issues.

10 Debug Port

10.1 Logic Analyzer Interface (LAI)

Information on logic analyzer interfaces for debugging system bus signals.

10.2 Mechanical Considerations

Discusses mechanical considerations for LAI installation and keepout volume.

10.3 Electrical Considerations

Covers electrical performance impacts of the LAI on the system bus.

11 EMI and Mechanical Design Considerations

11.1 Introduction

Introduces challenges of containing electromagnetic radiation from processors.

11.1.2 EMI Regulations and Certifications

Discusses EMC compliance and regulatory requirements for systems.

11.2 EMI Design Considerations

Describes design techniques applied to minimize EMI emissions.

11.2.1 Spread Spectrum Clocking (SSC)

Details SSC for reducing radiated emissions by frequency modulation.

12 Platform Power Delivery Guidelines

12.1 Customer Reference Board Power Delivery

Depicts the board power delivery architecture and requirements for components.

12.1.1 Processor Core Voltage

Details the processor core voltage power plane requirements and VRM compatibility.

12.1.2 2.5 V

Explains the 2.5 V power plane usage, requirements, and switching regulator.

12.1.3 1.25 V

Details the 1.25 V power plane generation and requirements.

13 Schematic Checklist

13.1 Processor Schematic Checklist

Provides a comprehensive checklist for processor schematic implementation.

13.2 MCH Schematic Checklist

Offers a checklist for the MCH schematic implementation.

13.3 Intel ICH3-S Schematic Checklist

Provides a checklist for the ICH3-S schematic implementation.

13.4 Intel 82870 P2 P64 H2 Schematic Checklist

Offers a checklist for the P64H2 schematic implementation.

14 Layout Checklist

14.1 Processor Checklist

Provides a comprehensive checklist for processor layout implementation.

14.2 Intel E7500 MCH Layout Checklist

Offers a checklist for the MCH layout implementation.

14.3 Intel ICH3-S Layout Checklist

Provides a checklist for the ICH3-S layout implementation.

15 Schematics