Intel Xeon - Power-Up and Power-Down Timing

Platform Power Delivery Guidelines
170 Design Guide
Figure 12-7. Power-Up and Power-Down Timing
3.3 VDC/SM_VCC
PWR_OK /
VID_OUT
OUTEN
VRM
PWRGD
Processor
PWRGOOD
Processor
RESET
T
0
=95% 3.3 volt level
Power Up
T
0
+ 10mS
> T
0
+ 100ms
1ms<T<10ms
3.3 VDC/SM_VCC
PWROK
OUTEN
Power Down
95% 3.3 volt level
Power Down Warning > 1ms