Intel Xeon User Manual

I/O Controller Hub
126 Design Guide
Note: Any EMI or ESD solution should be placed as close to the port as possible. For example, if using a
front-panel daughtercard, the EMI/ESD solution should be placed on the daughtercard.
9.4.6 USB Power Line Layout Topologies
The following is a suggested topology for power distribution of Vbus to USB ports. Circuits of this
type provide two types of protection during dynamic attach and detach situations on the bus: inrush
current limiting (droop), and dynamic detach flyback protection. These two different situations
require both bulk capacitance (droop) and filtering capacitance (for dynamic detach flyback
voltage filtering). It is important to minimize the inductance and resistance between the coupling
capacitors and the USB ports. That is, capacitors should be placed as close as possible to the port,
and the power-carrying traces should be as wide as possible, preferably a plane.
9.5 Intel
®
ICH3-S SMBus/SMLink Interface
The SMBus interface on the ICH3-S uses two signals, SMBCLK and SMBDATA, to send and
receive data from components residing on the bus. These signals are used exclusively by the
SMBus Host Controller. The SMBus Host Controller resides inside the ICH3-S. If the SMBus is
used only for the SPD EEPROMs (one on each DIMM), both signals should be pulled up with a
4.7 kΩ
± 5% resistor to VCC_3.3.
The ICH3-S incorporates an SMLink interface supporting Alert on LAN*, Alert on LAN2*, and a
slave functionality. This interface uses two signals, SMLINK[1:0]. SMLINK0 corresponds to an
SMBus clock signal, and SMLINK1 corresponds to an SMBus data signal. These signals are part
of the SMBus Slave Interface.
For Alert on LAN functionality, the ICH3-S transmits heartbeat and event messages over the
interface. When using the 82562EM Platform LAN Connect Component, the ICH3-S's integrated
LAN Controller will claim the SMLink heartbeat and event messages and send them out over the
network. An external, Alert on LAN2-enabled LAN Controller (i.e., Intel
®
82550) will connect to
the SMLink signals to receive heartbeat and event messages, as well as access the ICH3-S SMBus
Slave Interface. The slave interface function allows an external microcontroller to perform various
functions. For example, the slave write interface can reset or wake a system, generate SMI# or
interrupts, and send a message. The slave read interface can read the system power state, read the
watchdog timer status, and read system status bits.
Figure 9-6. Suggested USB Downstream Power Connection
Port1
Port2
G
G
n
n
d
d
V
V
c
c
c
c
4
4
1
1
47 pF
Thermistor
220 uF
G
G
n
n
d
d
V
V
c
c
c
c
4
4
1
1
47 pF
5V
5V
Switch
5V Sus

Intel Xeon Specifications

General

Brand	Intel
Model	Xeon
Category	Processor
Language	English