Design Guide 73
Memory Interface Routing Guidelines
6.3 Command Clock Routing
Only one differential clock pair is routed to each DIMM connector because the MCH only supports
registered DDR DIMMs. All CMDCLK/CMDCLK# termination is on the DIMM modules. Route
each clock and its compliment adjacent to each other. The two complimentary signals (e.g.,
CMDCLK0 and CMDCLK0#) must be length matched to each other within ± 2 mils. Excluding
breakout, the maximum recommended layer changes is one. Ensure that the reference plane does
not change when switching layer.
NOTES:
1. CMDCLK/CMDCLK# must be matched to within ± 2 mils using package trace length
compensation
.
2. The total trace length difference of any two CMDCLK/CMDCLK# pairs cannot exceed 4 inches for timing
reasons.
3. For 3-DIMM solutions, treat the CMDCLK3/CMDCLK3# pair as a no connect.
4. Indicated lengths measure from the MCH pin to the DIMM connector pin.
Table 6-4. Command Clock Pair Routing Guidelines
Parameter Intel
®
E7500 Reference
Signal Group CMDCLK[3:0], CMDCLK[3:0]#
Topology Point to point Figure 6-7
Reference Plane Ground Figure 6-8
Differential Trace Impedance (Zo) 100
Ω ± 10% Figure 6-8
Nominal Trace Width 5 mil Figure 6-8
Trace Spacing to Complement 5 mil Figure 6-8
Trace Spacing to Other Traces 20 mil Figure 6-8
Trace Length – MCH to DIMM1 2.1” to 10.0” Figure 6-7
Trace Length – MCH to DIMM2 2.1” to 10.0” Figure 6-7
Trace Length – MCH to DIMM3 2.1” to 10.0” Figure 6-7
Trace Length – MCH to DIMM4 2.1” to 10.0” Figure 6-7
MCH Breakout Guidelines 5/5, < 500 mil
Length Tuning Requirements CMDCLK to CMDCLK#: ± 2 mil
CMDCLK pair to pair: within ± 4.0 in.
CMDCLK pair to DQS pair: ± 1.75 in.
CMDCLK pair to Source Clocked Signal: ± 2.0 in.
Figure 6-7
Figure 6-6
Figure 6-9
Figure 6-7. Command Clock Topology
DIMMs
CMDCLK0 & CMDCLK0#
MCH
CMDCLK1 & CMDCLK1#
CMDCLK2 & CMDCLK2#
CMDCLK3 & CMDCLK3#
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