Intel Xeon User Manual

Memory Interface Routing Guidelines
74 Design Guide
NOTE: The Intel E7500 MCH may also use a 5 mil space between CMDCLK complements.
NOTES:
1. Indicated lengths measure from the MCH die pad to the DIMM connector pin.
Figure 6-8. Trace Width/Spacing for CMDCLK/CMDCLK# Routing
Core 5.2 mil
Dielectric 9.6 mil
2.1 mil (1 oz + plating)
Power
Dielectric
Power
Dielectric
Ground
Main Core
Dielectric
Core
Ground
Dielectric
Core
1.4 mil (1 oz)
1.4 mil (1 oz)
1.4 mil (1 oz)
1.4 mil (1 oz)
1.4 mil (1 oz)
1.4 mil (1 oz)
2.1 mil (1 oz + plating)
Core 5.2 mil
Dielectric 4.3 mil
Core 14.0 mil
Dielectric 9.6 mil
Dielectric 4.3 mil
Layer 1
Layer 2
Layer 3
Layer 4
Layer 5
Layer 6
Layer 7
Layer 8
CMDCLK CMDCLK#
CMDCLK#CMDCLK
CMDCLK CMDCLK#
CMDCLK
5 mil
CMDCLK#
7 mil
Signal
Signal
Signal
Signal
5 mil 20 mil 5 mil
Figure 6-9. Length Matching Requirements for Source Clocked Signal, CKE, and CS[7:0]#
MCH
DIMM
CMDCLK length = x
CMDCLK# length = x
Shortest CTRL length = x - 2.0"
Longest CTRL length = x + 2.0"

Intel Xeon Specifications

General

Brand	Intel
Model	Xeon
Category	Processor
Language	English