Intel Xeon - Intel E7500 Chipset-Based System Clocking Diagram

Design Guide 37
Platform Clock Routing Guidelines
Figure 4-1. Intel
®
E7500 Chipset-Based System Clocking Diagram
D
I
M
M
D
I
M
M
D
I
M
M
D
I
M
M
D
I
M
M
D
I
M
M
D
I
M
M
D
I
M
M
CLK66
CLK33_ICH3-S
Super I/O
FWH
P
C
I
P
C
I
P
C
I
P
C
I
32 bit
33MHz
CPU / CPU# (4)
PCIF (3)
PCI (7)
66BUF (5)
CLK33 x7
CLK33 (x5)
DIMMclk (x4 pr.)
DDR
Channel A
MCH
ITP
Processor
Processor
Intel
®
ICH-S
CK408B
Intel
®
P64H2
P
C
I
P
C
I
P
C
I
P
C
I
P
C
I
P
C
I
P
C
I
P
C
I
PCIclk
x7
P
C
I
P
C
I
P
C
I
P
C
I
P
C
I
P
C
I
P
C
I
P
C
I
P
C
I
P
C
I
P
C
I
P
C
I
P
C
I
P
C
I
P
C
I
P
C
I
Host_CLK
DDR
Channel B
DIMMclk (x4 pr.)
PCIclk
x7
PCIclk
x7
PCIclk
x7
PCIclk
x7
PCIclk
x7
USBCLK
USB-48MHz (1)
CLK14
REF0 (1)
CLK66
x3
BMC
P64H2 P64H2