Introduction
22 Design Guide
1.3.2.2 I/O Controller Hub 3 (Intel
®
ICH3-S)
The I/O Controller Hub (ICH3-S) provides the legacy I/O subsystem for E7500 chipset-based
platforms. Additionally, it integrates many advanced I/O functions. The ICH3-S includes the
following features:
• Provides HI1.5 Connection to MCH:
— 266 MB/s point-to-point connection for ICH3-S with parity protection.
— 8-bit wide, 66 MHz base clock, 4X data transfer.
— Parallel termination mode for longer trace lengths.
— 64-bit inbound addressing, 32-bit outbound addressing.
• 2 channel Ultra ATA/100 bus master IDE controller.
• 3 Universal Host Controller Interface (UHCI) USB 1.1 compliant host controllers
(Capabilities for six ports).
• I/O APIC.
• System Management Bus (SMBus) Specification, Version 1.1 compliant controller.
• LPC interface.
• AC '97 Component Specification, Revision 2.2 compliant interface.
• PCI Local Bus Specification, Revision 2.2 compliant interface.
• Integrated LAN Controller.
1.3.2.3 PCI/PCI-X 64-bit Hub 2 (Intel
®
82870P2 P64H2)
The P64H2 provides PCI/PCI-X, high-performance I/O capability on E7500 chipset based
platforms. Each P64H2 component includes:
• 16-bit, HI2.0 Connection to MCH:
— 1 GB/s point-to-point connection for I/O bridges with ECC protection.
— 16-bit wide, 66 MHz base clock, 8X data transfer.
— Parallel termination mode for longer trace lengths.
— 64-bit inbound addressing, 32-bit outbound addressing.
• Two Independent, 64-bit PCI/PCI-X Interfaces:
— PCI-X Specification, Revision 1.0a compliant.
— PCI Local Bus Specification, Revision 2.2 compliant.
— PCI-PCI Bridge Architecture Specification, Revision 1.1 compliant.
— PCI Hot Plug Specification, Revision 1.1 compliant.
— One PCI Hot Plug Controller (PHPC) per PCI/PCI-X interface.
— One IOxAPIC per PCI/PCI-X Interface (16 external, 8 internal interrupts).
— SMBus target for access to all internal PCI registers.
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