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Intel Xeon - Hub Interface 1.5 Decoupling Guidelines

Intel Xeon
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Hub Interface
92 Design Guide
7.3.4 Hub Interface 1.5 Decoupling Guidelines
To improve I/O power delivery, use two 0.1 µF capacitors per each component (i.e., the ICH3-S
and MCH). These capacitors should be placed within 150 mils of each package, adjacent to the
rows that contain the hub interface. If the layout allows, wide metal fingers running on the VSS
side of the board should connect the VCC_1.8/VCC_1.2 side of the capacitors to the VCC_1.8/
VCC_1.2 power pins. Similarly, if layout allows, metal fingers running on the VCC_1.8/VCC_1.2
side of the board should connect the ground side of the capacitors to the VSS power pins.

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